原创 FPGA读写2PORTRAM过程分析4

从寄存器配置中可以看出FLAGB 代表EP6的FULL标志，FLAGC代表EP2的EMPTY标志，而且都是低电平有效，就是说如果FLAGB输出低电平，代表EP6FIFO是FULL的。默认的话EP2是OUT,EP6是IN.

从WRITE READY 到WRITE这状态跳转很繁琐，我具体说一下，

首先，我们的程序是经过读USBFIFO，然后写SRAM，现在执行到这里。

FLAGB=1，EP6FIFO不满，执行

if (datacnt==sram_a_o)

         begin

          data_wr<=sram_d_o;

         end

ioRDY1_SLWRn<='b0;

ioRDY0_SLRDn<='b1;

STATE<=WRITE;

状态跳转到WRITE，执行下面语句，

ioRDY1_SLWRn<='b1;

ioRDY0_SLRDn<='b1;

if(sram_a_o!=ADDR_FULL+1)  //SRAM_A_0===?1000

         begin

                   sram_a_o<=sram_a_o+1;

                   datacnt<=datacnt+1;

                   sram_wren<='b0;                                //将数据写到FIFO中

                   sram_rden<='b1;

                   STATE<=WRITE_READY;

         End

然后再跳转到WRITE_READY,直到我们将EP6FIFO填满，现在的数据是什么不重要，只是为了填满FIFO，使得FLAGB为低电平。大约写256次，因为数据是16位，FIFO大小是512字节。现在执行下面函数

if (FFlagA==0)

         begin

                   datacnt<=datacnt+1;

                   fifodata[datacnt-sram_a_o]<=sram_d_o;

                   FFlagA<=FFlagA+1;

         end

                  else

                            fifodata[datacnt-sram_a_o]<=sram_d_o;

                            STATE<=WRITE_READY;

注意这里把DATACUT加一，但是没有将SRAM_A_O加一，也就是它们不再相等了。执行结束，重新跳转到WRITE_READY，执行下面的语句，else后面的语句，黄色覆盖的部分。

if (datacnt==sram_a_o)

         begin

                   data_wr<=sram_d_o;

         end

         else

           begin

                  fifodata[datacnt-sram_a_o]<=sram_d_o; 

                  fifodata[datacnt-sram_a_o-1]<=fifodata[datacnt-sram_a_o];

                  data_wr<=fifodata[datacnt-sram_a_o-1];

                  atacnt<=datacnt-1;

           end

ioRDY1_SLWRn<='b0;

ioRDY0_SLRDn<='b1;

STATE<=WRITE;

End

然后再跳转到WRITE状态，然后DATACNT和SRAM_A_O又相等了，然后重复上面提到的过程。直到SRAM_A_O=0X1000，然后写FIFO的流程才结束。

真是麻烦的，我都看得眼花了，估计还有分析不对的地方，以后再慢慢修改吧。

WRITE:

                   begin

                            ioRDY1_SLWRn<='b1;

                            ioRDY0_SLRDn<='b1;

                            if(sram_a_o!=ADDR_FULL+1)  //SRAM_A_0===?1FFF

                                     begin

                                     sram_a_o<=sram_a_o+1;

                                     datacnt<=datacnt+1;

                                     sram_wren<='b0;

                                     sram_rden<='b1;

                                     STATE<=WRITE_READY;

                                     end

                            else

                                     begin                          

                                     sram_wren<='b0;

                                     sram_rden<='b0;

                                     STATE<=WRITE_END;

                                     end 

                   end

WRITE_END:

                   begin

                   wr_flag='b0;

                   ioRDY1_SLWRn<='b1;

                   ioRDY0_SLRDn<='b1;               

                   sram_a_o<='h1fff;

                   datacnt<='h1fff;

                   sram_wren<='b0;

                   sram_rden<='b0;

                   oPA4_FIFO0<='b1;

                   oPA5_FIFO1<='b1;

                   STATE<=IDLE;

                   end

         default:

                   STATE<=IDLE;

         Endcase

这2个状态就很简单了，不用多说了。