原创 Signals on port captured by SignalTapII inverted

Q:

I added a output pin as a node to SignalTap II, and fount that signal on this pin captured by SignalTapII is an inverted one of actual signal.

If that a internal node of FPGA is inverted can be regarded as a result of synthesis, how to explain the inverting on pins?

A:

The registers in the device core hardware can only power up or reset to 0 in all Altera devices. For the register which are required to power up or reset with a logic level High in the design, the Compiler performs an optimization referred to as NOT Gate Push-Back on the registers. NOT Gate Push-Back is a synthesis option, it adds an inverter to the input and the output of the register so that the reset and power-up conditions will appear to be high and the device operates as expected. The register itself actually still powers up low, but the register output is inverted so the signal arriving at all destinations is high.

If the register driving this pin is inverted, it is possible that the inverter after register is implemented in the I/O cell. When you add the output pin in SignalTapII, it cannot be routed into the I/O cell since the device resource limitation, only the signal before I/O cell can be connected. So the signal in SignalTapII is inverted with the output pin. To verify the issue, you can choose to locate the output pin to Resource Property Editor window and trace back to see where the SignalTapII probe is connected. If you need any further help, please let me know.