原创 VHDL语言在实现FPGA驱动LED静态显示中的应用实例

VHDL语言在实现FPGA驱动LED静态显示中的应用实例<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

--文件名：decoder.vhd

--功能：译码输出模块，LED为共阳接法

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is

Port (seg:in std_logic_vector(3 downto 0 );   --四位二进制码输入

q3:out std_logic_vector(6 downto 0) );   --输出LED七段码

end decoder;

architecture Behavioral of decoder is

begin

process(seg)

begin

case seg is

when "0000" => q3<="0000001";--0  

when "0001" => q3<="1001111";--1

when "0010" => q3<="0010010";--2

when "0011" => q3<="0000110";--3

when "0100" => q3<="1001100" --4

when "0101" => q3<="0100100";--5

when "0110" => q3<="0100000";--6

when "0111" => q3<="0001111";--7

when "1000" => q3<="0000000";--8

when "1001" => q3<="0000100";--9

when others => q3<="1111111";

end case;

end process;

end Behavioral;

   功能实现模块。