原创 TESTBENCH 语法参考(1）

TEST BENCH 语法参考
以下举例了一些常用的TESTBENCH语法

always
block
counter
for
forever
fulladd
func2
imp_del
initial
momory
mux1
mux2
mux4
repeat
sig-ctrl
task
while

---------------------------------------------------

module clock_gen;

reg clock;

//Initialize clock at time zero
initial
clock = 1'b0;

//Toggle clock every half cycle (time period = 20)
always
#10 clock = ~clock;

initial
#1000 $finish;

endmodule

return

--------------------------------------------

module dummy;
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;

//All behavioral statements must be inside an initial or always block
initial
begin
        x = 0; y = 1; z = 1; //Scalar assignments
        count = 0; //Assignment to integer variables
        reg_a = 16'b0; reg_b = reg_a; //initialize vectors

        reg_a[2] = #15 1; //Bit select assignment with delay
        reg_b[15:13] = #10 {x, y, z};//Assign result of concatenation to
                                     // part select of a vector
        count = count + 1; //Assignment to an integer (increment)
end

initial
        $monitor($time,
        " x = %b, y = %b, z = %b, count = %0d, reg_a = %x, reg_b = %x",
     x, y, z, count, reg_a, reg_b);

endmodule

return

------------------------------------------------------

//Binary counter
module counter(Q , clock, clear);

// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;

always @( posedge clear or negedge clock)
begin
if (clear)
Q = 4'd0;
else
//Q = (Q + 1) % 16;
Q = (Q + 1) ;
end

endmodule

// Top level stimulus module
module stimulus;

// Declare variables for stimulating input
reg CLOCK, CLEAR;
wire [3:0] Q;

initial
$monitor($time, " Count Q = %b Clear= %b", Q[3:0],CLEAR);

initial
$gr_waves( "clk", CLOCK,
"Clear", CLEAR,
"Q", Q[3:0],
"Q0", Q[0],
"Q1", Q[1],
"Q2", Q[2],
"Q3", Q[3]);

// Instantiate the design block counter
counter c1(Q, CLOCK, CLEAR);

// Stimulate the Clear Signal
initial
begin
CLEAR = 1'b1;
#34 CLEAR = 1'b0;
#200 CLEAR = 1'b1;
#50 CLEAR = 1'b0;
end

// Setup the clock to toggle every 10 time units
initial
begin
CLOCK = 1'b0;
forever #10 CLOCK = ~CLOCK;
end

// Finish the simulation at time 200
initial
begin
#400 $stop;
end

endmodule

return

--------------------------------------------

module counter;

integer count;

initial
for ( count="0"; count < 128; count = count + 1)
$display("Count = %d", count);

endmodule

return

---------------------------------------------------

module synchronize;

//Example 2: Synchronize two register values at every positive edge of
//clock
reg clock;
reg x, y;

initial
begin
clock = 1'b0;
x = 1'b0;
y = 1'b0;
#100000 $finish;
end

always #5 clock = ~clock;
always #11 y = ~y;

initial
forever @(posedge clock) x = y;

endmodule

return

-------------------------------

// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations
output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;

// Specify the function of a full adder
assign #2 {c_out, sum} = a + b + c_in;

endmodule

// Define the stimulus (top level module)
module stimulus;

// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4
fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

// Setup the monitoring for the signal values
initial
begin
$monitor($time," A= %b, B=%b, C_IN= %b,, C_OUT= %b, SUM= %b\n",
A, B, C_IN, C_OUT, SUM);
end

return

--------------------------------------------------

//Define a module which contains the function shift
module shifter;

//Left/right shifter
`define LEFT_SHIFT 1'b0
`define RIGHT_SHIFT 1'b1
reg [31:0] addr, left_addr, right_addr;
reg control;

initial
begin
$monitor("%0d left= %h right = %h addr = %h",
$time, left_addr, right_addr, addr);

#1 addr = 32'h3456_789a;
#10 addr = 32'hc4c6_78ff;
#10 addr = 32'hff56_ff9a;
#10 addr = 32'h3faa_aaaa;
end

//Compute the right and left shifted values whenever
//a new address value appears
always @(addr)
begin
//call the function defined below to do left and right shift.
left_addr = shift(addr, `LEFT_SHIFT);
right_addr = shift(addr, `RIGHT_SHIFT);
end

//define shift function. The output is a 32-bit value.
function [31:0] shift;
input [31:0] address;
input control;
begin
//set the output value appropriately based on a control signal.
shift = (control == `LEFT_SHIFT) ?(address << 1) : (address >> 1);

end
endfunction

endmodule

return

-------------------------------------------

module implicit_delay (out, in1, in2);

output out;
input in1, in2;

wire #10 out = in1 & in2; // Delay in a continuous assign

endmodule

module stimulus;

wire OUT;
reg IN1, IN2;
initial
begin
IN1 = 0; IN2= 0;
#20 IN1=1; IN2= 1;

#40 IN1 = 0;

#40 IN1 = 1;
#5 IN1 = 0;
#150 $stop;
end

initial
$gr_waves("out", OUT, "in1", IN1, "in2", IN2);

implicit_delay rd1(OUT, IN1, IN2);

endmodule

return

---------------------------------------

module stimulus;

reg x,y, a,b, m;

initial
m = 1'b0; //single statement; does not need to be grouped

initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end

initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end

initial
#50 $finish;

endmodule

return

----------------------------------------

module test;

reg [7:0] memory[0:7]; //declare an 8 bit memory with 8 locations
integer i;

initial
begin
//read memory file. address locations given in memory
$readmemb("init.dat", memory);
//display contents of initialized memory
for(i=0; i < 8; i = i + 1)
$display("Memory [%0d] = %b", i, memory);
end