方法1:
module led(CLOCK_50,KEY,LEDG,LEDR);
input CLOCK_50;
input [3:0] KEY;
output [8:0] LEDG; // LED Green[8:0]
output [17:0] LEDR; // LED Red[17:0]
reg [31:0] Cont;
always@(posedge CLOCK_50 or negedge KEY[0])
begin
if(!KEY[0])
Cont <= 0;
else
Cont <= Cont+1;
end
assign LEDR = { Cont[25:23],Cont[25:23],Cont[25:23],
Cont[25:23],Cont[25:23],Cont[25:23] };
assign LEDG = { Cont[25:23],Cont[25:23],Cont[25:23] };
endmodule
方法2.
module led(CLOCK_50,LEDR,KEY,LEDG);
input CLOCK_50;
input [3:0] KEY;
output[17:0] LEDR;
output [7:0] LEDG;
reg[17:0] LEDR;
reg[7:0] LEDG;
reg [31:0] Cont;
initial
begin LEDR="5"'h00001;
LEDG="8"'b10000000;
end
always@(posedge CLOCK_50 or negedge KEY[0])
begin
if(!KEY[0])
Cont <= 0;
else
Cont <= Cont+1;
end
assign clk_divide=Cont[23];
always @(negedge clk_divide)
begin
// Cont <= 0;
if(LEDR==5'h20000)LEDR=5'h00001;
else
LEDR="LEDR"<<1;
if(LEDG==8'b00000001)LEDG=8'b10000000;
else
LEDG="LEDG">>1;
end
endmodule
用户289871 2010-7-21 16:56
用户422901 2010-7-1 11:20