原创 Second-generation Serial Challenges

        At the data rates next-generation serial standards operate, analog anomalies of the signal have a greater impact on signal integrity and quality than ever before. Conductors in signal pathways, including circuit board traces, vias, connectors, and cabling, exhibit greater transmission line effects with return losses and reflections that degrade signal levels, induce skewing, and add noise.

Gigabit Speeds

<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

With each increase in transfer rates of the standards, the UI shrinks, and the tolerances in transmitter signal quality and receiver sensitivity become tighter. Low-voltage differential signals and multi-level signaling are more vulnerable to signal integrity issues, differential skew, noise, and inter-symbol interference (ISI) as speeds increase. There is greater susceptibility to timing problems, impedance discontinuities between a transmitter and receiver, and system level interaction between hardware and software. Multi-lane architectures amplify design complexity and potential for lane skew timing violations and crosstalk.

Jitter

Today’s higher data rates and embedded clocks mean greater susceptibility to jitter, degrading bit error rate (BER) performance. Jitter typically comes from crosstalk, system noise, simultaneous switching outputs, and other regularly occurring interference signals. With faster rates, multi-lane architectures, and more compact designs, there are more opportunities for all these events to affect data transmission in the form of signal jitter.

Transmission Line Effects

The signal transmitter, conductor pathways, and receiver constitute a serial data network. Buried in that network are distributed capacitance, inductance, and resistance that have diverse effects on signal propagation as frequencies increase. Transmission line effects rise from this distributed network and can significantly impact signal quality and lead to data errors.

Noise

Noise is unwanted aberrations in the amplitude domain that appear in the signal. Noise comes from both external sources, such as the AC power line, and internal sources, including digital clocks, microprocessors, and switchedmode power supplies. Noise can be transient or broadband

random noise and can lead to phase errors and signal integrity problems. Like jitter in the frequency domain, with faster signaling, noise in the amplitude domain adds variations that can have a critical impact on BER performance.

Compliance Testing

Serial standards normally include amplitude, timing, jitter, and eye measurements within their compliance testing specifications. The latest versions of some standards add focus, compared to previous versions, on SSC clocking, receiver sensitivity testing, and measurement of return loss and reflections on connectors, cables, and other pathways. Not all measurements are required for compliance with every standard.

Test points are specified in the standard’s unified test document or the specification itself.