原创 XILINX DDR 控制器约束问题的解决

ERROR:ConstraintSystem:58 - Constraint <NET<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

   "U_DDR_ctrl/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" TNM_NET = "fifo_we_clk";> [VIDEO_SYNTH.ucf(2)]: NET

   "U_DDR_ctrl/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_ins

   t/clk" does not match any design objects.

这个错误是最前面的约束错误，也意思是找不到匹配的对象。检查路径没有错误，把该约束内容删除，打开空白时序约束编辑器，进行TNM_NET约束，查找网点，未找到CLK的信号，连CLK例化信号dqs_delayed_col1_n、dqs_delayed_col0也没找到，而发现在它的上一级模块中，如果对她们进行约束不能串过前一级还不能对指定的路径进行约束，寻求改信号名或更改路径方法约束较麻烦，就暂时放下。经过网络搜索也没有找到解决办法。这个问题困绕着两天没有解决。突然想起直接把前述的错误提示NET "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk"输入GOOGLE搜索（GOOGLE在搜索这方面还是很强大的，百度就不行了，题外话，呵呵），终于找到问题解决方法了。原来要设置综合属性保持模块层次设置为soft,该设置意思是综合保持层次结构属性，但布局布线就不保持。还有YES和NO，自然明白其意义了，就不说了，缺省为NO。这样，问题迎刃而解，所有的约束都能修改好。

原文如下：

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-3E-DDR-MIG/m-p/32967/page/2

05-17-2009 04:49 AM

Hi Sanjaac,

thanks for your reply, my application is for radio  porpouse: I want to store into the ddr the samples from an external adc and donwload or elaborate on my pc.

I see the ug086 and with your post I study your code, I try to start with init sequence to see the effect on ddr but I found this problems:

1) I cannot simulate with modelsim (there is an error and I haven't (I think) any infos where the error is)

2) When I try to "translate" I get a lot of error ...

Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:58 - Constraint <NET
   "U_4/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk"
   TNM_NET = "fifo_we_clk";> [ddrctrl_tester.ucf(17)]: NET
   "U_4/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk"
   does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_WE_CLK" = FROM "dqs_clk"
   TO "fifo_we_clk"  5 ns DATAPATHONLY;> [ddrctrl_tester.ucf(18)]: Unable to
   find an active 'TimeGrp' or 'TNM' or 'TPSync' or 'TPThru' constraint named
   'fifo_we_clk'.

ERROR:ConstraintSystem:58 - Constraint <NET
   "U_4/top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/c
   lk" TNM_NET = "fifo_waddr_clk";> [ddrctrl_tester.ucf(20)]: NET
   "U_4/top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/c
   lk" does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_WADDR_CLK" = FROM
   "dqs_clk" TO "fifo_waddr_clk"  5 ns DATAPATHONLY;> [ddrctrl_tester.ucf(21)]:
   Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' or 'TPThru'
   constraint named 'fifo_waddr_clk'.

ERROR:ConstraintSystem:59 - Constraint <INST
   "U_4/infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;>
   [ddrctrl_tester.ucf(262)]: INST "U_4/infrastructure_top0/cal_top0/cal_ctl0"
   not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

it's very strange because when I compile the code into your rar archive everything goes well...I have check the error and the "U_4/infrastructure_top0/cal_top0/cal_ctl0" is present.

What can I do?

Hi,

The two possible causes of your "problem", at least as far as I can figure out, are:

- Different naming in the structure. You need to modify the U_4/etc... in the .ucf stuff to match the names of the instance as you have actually named them in your code, structural one. Indeed I had to do it by hand from the MIG generated UCF; if I did not do so I got the same kind of messages.

- Beware of the synthesis options. Chances are that you do not have kept the "Keep hierarchy" setting, and the synthesizer is throwing those signal names away. This is very needed for the DDR controller itself; in my project I set to "Soft" and it works. Whenever I set "No" to keep the hierarchy, I had the same messages as you are having.

Good luck!