module Freq_div(clk,rst,out);
input clk;
input rst;
output out;
reg out1;
reg out2;
reg[1:0] cnt1;
reg[1:0] cnt2;
always@(posedge clk or negedge rst)
if(!rst)
begin
cnt1<=2'b00;
out1<=1'b0;
end
else if(cnt1==2'b10)
begin
cnt1<=2'b00;
out1<=out1;
end
else
begin
cnt1<=cnt1+1'b1;
out1<=~out1;
end
always@(negedge clk or negedge rst)
if(!rst)
begin
cnt2<=2'b00;
out2<=1'b0;
end
else if(cnt2==2'b10)
begin
cnt2<=2'b00;
out2<=out2;
end
else
begin
cnt2<=cnt2+1'b1;
out2<=~out2;
end
assign out=out1 | out2;
endmodule
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