原创 带FIFO的UART 顶层

input       clk;
  input       rst;
  input [1:0] baud_sel; 
  input       rx;
  output      tx;
 
 
  wire tx_clk;
  wire rx_clk;
 
  baud_gen U_GEN(
                .clk(clk),
                .rst(rst),
                .baud_sel(baud_sel),
                
                .tx_clk(tx_clk),
                .rx_clk(rx_clk)
                );

  wire [7:0] rece_data;
  wire       rece_rdy ;  
  uart_rx U_RX(
              .clk    (rx_clk   ),
              .rst    (rst      ),
              .rx     (rx       ),
              .dataout(rece_data),
              .rdsig  (rece_rdy ),
             
              .dataerror(),
              .frameerror()
              );
  //judge the dly and get start read signal          
  reg [9:0]cont_rx;
  always @(posedge rx_clk)
  begin
    if(rst)
      cont_rx <= 10'd0;
    else if(rece_rdy)
      cont_rx <= 10'd0;
    else if (cont_rx == 10'd672) //168*4
      cont_rx <= cont_rx;
    else
      cont_rx <= cont_rx + 1'b1;
  end
 
  //get the counter of rece_rdy;
  reg [4:0] rdy_cnt;
  always @(posedge rx_clk)
  begin
    if(rst)
      rdy_cnt <= 5'd0;
    else if(rece_rdy)
      rece_rdy <= rece_rdy + 1'b1;
    else if(cont_rx == 10'd672)
      rece_rdy <= 5'd0;
    esle ;
  end
 
  reg wren;
  reg [7:0] fifo_din;
  always @(posedge rx_clk)
  begin
   if(rst)
    begin
     fifo_din <= 8'd0;
     wren     <= 1'b0;
    end
   else
    begin
     fifo_din <= rece_data;
     wren     <= rece_rdy ;
     end
  end
 
 
  //Depth 128
  wire [7:0] rd_fifo;
  wire fifo_full;
  wire fifo_empty;
 uart_fifo U_RX_FIFO(
            .rst  (rst     ), 
            .wr_clk(rx_clk  ),                   
            .rd_clk(tx_clk  ),                   
            .din   (fifo_din), 
            .wr_en (wren    ),
                                
            .rd_en (cont_rx == 10'd672 & (~fifo_empty )),                    
            .dout  (rd_fifo                            ),                          
            .full  (fifo_full                          ),                          
            .empty (fifo_empty                         )                     
           );                                
 
 reg [7:0] mem [127:0];
 integer i;
 always @(posedge tx_clk)
 begin
  if(rst)
   for(i=0; i<16; i=i+1)
    mem <=8'd0;
  else if(cont_rx == 10'd672 & (~fifo_empty ))
   begin
    mem[0] <= rd_fifo;
    for(i=1; i<16; i=i+1)
     mem = mem[i-1];
   end
  else;
 end         
             
 
      
  uart_tx U_TX(
              .clk    (tx_clk ),
              .rst    (rst    ),
              .data_in(data_in),
              .en (en),
              .txd(txd),
              .txd_busy()
              );