原创 我来了

module pechar(CLKIN,CLKOUT ,H_SIN,V_SIN,CHAR,NBLS,CE,WE,OE,ADDR,XDATA,CHAR1);
 input CLKIN,H_SIN,V_SIN;
 output CLKOUT,CHAR,CE,WE,OE,CHAR1;
 reg    CLKOUT,CHAR,CE,WE,OE,CHAR1;
 output [1:0] NBLS;
 reg    [1:0] NBLS;
 output [17:0] ADDR;
 reg    [17:0] ADDR;
 input  [15:0] XDATA;
 reg    [5:0] counter; 
 always @(posedge CLKIN)
 begin
  NBLS<=3;
  WE<=1;
  CE<=0;
  OE<=0;
  CLKOUT<=!CLKOUT;
  CHAR<=H_SIN&&V_SIN;
  counter<=counter+1;
  
  case (counter)
  
   0:
   begin
   if(ADDR>18'hffff)
   begin
    ADDR<=0;
   end
   else
   begin
    ADDR<=ADDR+2;
   end
   end
   1: CHAR1<=XDATA[0];
   3: CHAR1<=XDATA[1];
   5: CHAR1<=XDATA[2];
   7: CHAR1<=XDATA[3];
   9: CHAR1<=XDATA[4];
   11: CHAR1<=XDATA[5];
   13: CHAR1<=XDATA[6];
   15: CHAR1<=XDATA[7];
   17: CHAR1<=XDATA[8];
   19: CHAR1<=XDATA[9];
   21: CHAR1<=XDATA[10];
   23: CHAR1<=XDATA[11];
   25: CHAR1<=XDATA[12];
   27: CHAR1<=XDATA[13];
   29: CHAR1<=XDATA[14];
   31: CHAR1<=XDATA[15];
   32:CHAR1<=1;
   default:CHAR1<=0;
    
  endcase
  
  
 end

endmodule