One of the most interesting architectural decision in the design project is how to calculate the depth of a FIFO. FIFO is an intermediate logic where the data would be buffered or stored . Smaller FIFO depth can cause overflow scenario and cause a data loss.
For worst case scenario, difference in the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered for calculating the depth of the FIFO.
Any Asynchronous FIFO has a write frequency and a read frequency. Assume that the write frequency (Fw) is faster than read frequency (Fr).
Scenario 1:
Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and read respectively.
Scenario 2:For worst case scenario, difference in the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered for calculating the depth of the FIFO.
Any Asynchronous FIFO has a write frequency and a read frequency. Assume that the write frequency (Fw) is faster than read frequency (Fr).
Scenario 1:
Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and read respectively.
Consider the case of a FIFO where the 'Fw' is 100 MHz and 50 words are written into the FIFO in 100 clocks while the 'Fr' is 50 MHz and one word is read out every clock.
In the worst case scenario, the 50 words are written into the FIFO as a burst in 500 ns. In the same time duration, the read side can read only 25 words out of the FIFO. The remaining 25 words are read out of the FIFO in the 50 idle write clocks. So the depth of the FIFO should be at least 28. (Three clock cycles are for synchronizer latency).
BTW,i think we can also calculate fifo size as follows:
Bandwith of bytes that the receiver can read
- 上一篇： 怎样成为优秀的电子工程师-【强烈推荐】转
- 下一篇： FPGA和CPLD基本结构
EE直播间
更多
-
精密半导体参数测试解决方案 直播时间： 01月08日 10:00
关闭
站长推荐
/3 
/3
文章评论（0条评论）
登录后参与讨论