tag 标签: core

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  • 热度 3
    2019-10-13 19:11
    1354 次阅读|
    1 个评论
    《手把手教你设计CPU——RISC-V处理器篇》-- CPU是怎样炼成的
    首先感谢社区提供图书试读活动,能够让我有机会申请到这本期待已久的书 《 手把手教你设计 CPU——RISC-V 处理器篇》 。 之所以期待已久是因为,本书作者是一线工程师出身,工程师写的书往往理论内容少一些,读起来不会很枯燥,另一方面更加结合实际的开发和应用,会有很多的经验总结和分享,能够让读者学以致用,应用到工作和学习的实际项目中。 # 作为一名芯片公司的软件工程师,我对各种架构CPU和生态以及计算机各个方面的基础理论也稍有研究。 这本书主要以设计一颗RISC -V 的 MCU 为例,详细介绍了CPU是怎样炼成的。书中描述了设计过程中的重点环节和模块,并在Github开源了相应芯片蜂鸟E203的源码以及相关文档,项目地址为 https://github.com/SI-RISCV/e200_opensource ,读者可以结合源码仔细阅读书中相应章节。 什么是RISC -V? 简单来说,RISC -V 是一种最近几年比较热门的新的CPU架构,和x 86 和arm一样,它符合基本的CPU体系结构模型能够实现计算和控制功能。所不同的是它并非诞生于商业公司,而是由教育机构和开源社区合作实现并通过开源基金会管理。它能够为开发者提供开源 / 免费的指令集和CPU参考设计,并且是非常高效和先进的设计。 为什么选择 RISC-V 架构? 书中前两章很好的回答了这个问题。想当年,CPU界群雄并起,争霸江湖。但最终x 86 凭借w intel 建立的强大生态联盟,占领了PC和服务器市场。而arm则是凭借优秀的低功耗设计和不错的运气在智能机兴起时期,迅速占领了市场并不断加强生态建设建立自己的护城河。 但是这两种架构的指令集都是归商业公司所有,想要使用相关架构的CPU甚至基于指令集实现CPU都是收费的,而且使用上也有很多限制。Berkeley的同志们就是困扰于没有可靠的免费指令集可用,遂决定重新定义新的架构并基于此架构设计芯片。 从书中概括几个RISC -V 架构的主要特点: 架构简洁 :相比于x 86 和arm , 后两者都经历了多则数十年的发展,不断优化 / 增强的同时还要保持向前兼容,这样不断的打补丁就导致架构变的越来越臃肿,虽然众多优秀的工程师投入巨大精力使得性能仍然非常好,但是从设计者的角度,越来越难去把握其中的细节,有大量的坑在等着你,这一点从x 86 或者arm为架构出的errata文档就可以看出。RISC -V 因为吸取了大量先进的设计理念和经验,具备后发优势,没有历史包袱,架构更加简洁清晰,用作者的话说就是短小精悍。感兴趣的读者可以从基金会官网 https://riscv.org/ 或者本书项目的GitHub主页下载阅读架构文档。 模块化的指令集 :相比于arm架构 A / R / M 三个高中低架构互不兼容, RISC-V 能够使得用户灵活地选择不同个的模块进行组合,满足各种应用需求。如嵌入式选择 RV32IC ,高性能可选择 RV32IMFDC 等 扩展指令集 :用户可以根据需要扩展自己的指令子集, RISC-V 预留了大量的指令编码空间用于用户自定义扩展。为了狙击RISC -V ,arm最近也宣布在部分CPU内核引入自定义指令功能。 CPU长啥样? 书中蜂鸟E203 SOC和C ore 原理图如下: CPU C ore中主要包含取指器 / 译码器(也叫控制器) / 计算执行单元 (ALU) 和寄存器组,流水线的实现就是对这几个模块的硬件多次实现并行执行。 书中 7-10 章讲解了指令执行过程中各个步骤的硬件如何设计和优化,包括取指 / 译码 / 执行 / 交付和写回。 上层软件经过编译链接生成对应机器的字节码,CPU从相应地址根据指令长度依次取指执行。一切看上去很自然也很轻松,但是硬件设计上需要考虑很多问题,比如如何快速取值,如何处理非对齐指令和分支指令等。指令执行过程中会碰到流水线冲突和分支如何预测等更多问题,如何设计可靠的CPU确实需要非常多的经验积累,参考本书可以少走很多弯路。 Co re 中其他硬件模块还包括存储器接口 / 中断控制器,和其他可选的如FPU ( 浮点运算模块 ) 和trace接口等,参见书中相关章节。 这样我们就有了一个可以进行运算的Core。对于SOC来说,我们还需要片内总线进行core和外设的连接,常用的总线协议包括 AHB APB 等,蜂鸟E203中使用自定义总线协议ICB进行Co re 和存储器等外设的互联 书中第三部分具体讲解了如何在FPGA上运行和验证这颗 蜂鸟E203 SOC , 有FPGA硬件开发板并且熟悉verilog的同学可以按照书中的介绍对该芯片的开源代码进行仿真测试和运行。 最后附上arm Cortex M4 架构图做为对比学习
  • 热度 2
    2014-10-21 18:21
    546 次阅读|
    0 个评论
    Anyone knowledgeable of the specifications of telecom protocols will recognize that they are both detailed and complex. So it is surprising -- especially given the revelations of whistle blowers such as Edward Snowdon and the current cyber security fixation -- that the Optical Transport Network (OTN) does not inherently feature any encryption.   The OTN's evolution has seen the successful inclusion of Ethernet packets into the payload. Originally, the OTN was designed to transport SONET/SDH, but it has been adapted to work with the faster Ethernet standards.   There is growing interest among equipment vendors in the notion of adding encryption to provide privacy and tamper detection on OTN systems with minimal added latency. The growing use of networks for applications such as financial transactions is a key driver for this technology.     Encrypting an OTN system requires the equipment vendor to work closely with an intellectual property (IP) vendor for several reasons. First, the method of securely transmitting the encryption keys must be organized. Fortunately, unlike in many systems, the keys in OTN systems are updated fairly infrequently. This allows for pre-computation of some encryption parameters in software, rather than providing hardware to compute them on the fly, as would be necessary in a protocol such as MACsec or IPsec, in which keys can change for every packet. Another issue is to get an efficient, low-latency core to fit into the design. Nearly every system contains a programmable logic chip such as a field programmable gate array (FPGA) to handle a range of protocol, framing, control, and interfacing tasks. The encryption IP core can be included in the FPGA. Where sufficient spare resources exist, this can even be achieved without moving to a larger device.   Algotronix Ltd.'s recently released OTN encryption core offers an interesting solution. The UK vendor has carefully optimized the core to be compatible with the traffic characteristics of the OTN system, such as fixed packet length. As a result, the lookup table (LUT) usage of the duplex AES-GCM core for the OTN is half what would be necessary for a duplex AES-GCM implementation for encrypting and decrypting 10G Ethernet packets.   The core provides AES-GCM with 96-bit IV and a choice of 128-bit or 256-bit keys. This gives privacy as well as confirmation that the decrypted packet has not been altered, which is mandatory for many systems. Designers can use recent FPGA families supplied by all leading vendors and select from a number of implementation options. Another very useful option is the ability to drive the FPGA tools into using certain resource types for key blocks of the core. The AES system requires the creation of what are known as S-Boxes as a significant part of the total resource requirement. Enabling the design tools to favor logic or memory blocks for these elements can allow the design to fit into the available spare capacity and therefore to squeeze the encryption core into a tightly packed layout.   One special consideration for encryption IP relates to confidence that the security has not been compromised. A concern in any high-security design is to ensure that so-called Trojan Horse features have not been maliciously included. It is important, therefore, to select a reputable vendor whose source code can be carefully inspected. It greatly reduces the risk that anybody has contributed malicious code to, say, an open source project. Licensing source code, rather than just a netlist, gives users the option to analyze the design. It also reduces the burden and cost of a detailed analysis of all the security components in the system.   Verification is the number one headache in system design. AES with Galois/Counter Mode (AES-GCM) was standardized by the National Institute of Standards and Technology (NIST) with a number of different operating modes. The institute also provides a large number of tests with "known answer" patterns to be used in implementation validation. For validation, it is good to know that the core ships with a comprehensive test bench including a behavioral model of AES-GCM. Along with the Algotronix-supplied testbench code, the core can also be simulated in a self-checking configuration within the user design, where it checks its output against a behavioral model.   The introduction of an IP core optimized for OTN systems gives equipment manufacturers the opportunity to differentiate their products with cost-effective, low-latency security features.
  • 热度 3
    2012-12-8 10:30
    629 次阅读|
    2 个评论
    功能说明  处理器:FreeScale  i.MX535(1000Mhz)/i.MX536(800Mhz)  内存  :1024M Bytes DDR3  存储器:4G Bytese iNAND(SD接口),最大支持到 32GBytes   显示  :24-bit并行显示输出,up to 1600 x 1200, 24bpp,两路 18-bitLVDS输出  RTC   :  YES  WDT :  YES  UART :TTLlevel x 5  Ethernet LAN: 10/100Mbps BASE-T  USB 2.0 HOST:1  USB 2.0 OTG: 1     SD/MMC: 2   SATA: 1   SPI: 2   I2C: 2   CANBUS : 2(可选)   KeyPad : 5*5   Audio : 2 way out, Mic_in  供电: 3.3V-5.5V  OS: Linux 2.6.35,Android 尺寸:84X55mmm QQ:64909646  
  • 热度 1
    2012-12-8 10:28
    1020 次阅读|
    0 个评论
    主控 AT91SAM9X25   400M高速ARM926EJ核心; ◆ 单颗DDR2 SDRAM,128M ◆ 大容量板载电子盘,256M ◆ 优质2.54间距的插件,更低成本 ◆ 双路10M/100M以太网,板载PHY ◆ CPU内置7路RS232串口 ◆ 板载两路CAN 2.0B ◆ 板载IIS,IIC,SPI等外部接口 ◆ 支持SD卡接口,大容量存储; ◆ 高速USB 2.0 Device接口; ◆ 高速USB 2.0 Host接口; ◆ 核心板高集成度,可以直接应用,可根据客户定制主板; 尺寸55*55mm 如需要该核心板,请联系:QQ:64909646
  • 热度 1
    2012-10-15 20:11
    746 次阅读|
    0 个评论
    The recent news that their licensees have shipped 2 billion IP cores is obviously a reason for rejoicing at Tensilica's world-wide command center. So, if you have had occasion to stroll past Tensilica's corporate headquarters and RD center in Santa Clara, California, recently, you may have wondered at the "For Lease" sign planted firmly in front of the building.   What? How can this be? What is going on? In these days of doom and gloom, it's common to see this sort of thing and assume a worse-case scenario. But fear not my braves, because there is nothing to fear but fear itself (as my dear old dad used to tell me). A little bird tells me that things are going so swimmingly well at Tensilica that they've been hiring furiously, with the result that the current building is bursting at the seams (I hear dire tales of people working out of conference rooms and crammed into closets). Thus, on 20 October 2012 (just a few days' time as I pen these words), we will be seeing a mass exodus from Tensilica's current building as the little scamps all move down the road into a brand-spanking new facility.   If only I had the time, on moving day I would take a lawn chair and some cold drinks and ensconce myself on the lawn outside the new building and cheer them on their way. Sad to relate, however, I am up to my armpits in alligators fighting fires without a paddle (I never metaphor I didn't like), so I will just have to wish them all the best from the comfort of the pleasure dome (my office).  
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