标签: vhdl编程

library ieee ; use ieee.std_logic_1164.all; entity lamp is port (nrst : in std_logic; --negative shift_direction:in std_logic;--'1' for right ; '0' for left clk:in std_logic; Q : out std_logic_vector(7 downto 0) --controll 8 led lamp ); end lamp; architecture lamp of lamp is signal temp : std_logic_vector(7 downto 0); begin process(clk,nrst,shift_direction) begin if nrst='0' then temp(7 downto 0) ="10000000"; elsif clk'event and clk = '1' then if shift_direction = '1' then temp(7 downto 0) = temp(0) temp(7 downto 1) ; else temp(7 downto 0) = temp(6 downto 0) temp(7); end if; end if; q(7 downto 0)=temp(7 downto 0); end process; end lamp;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --************************* ENTITY counter10 is PORT( CP:IN Std_Logic; Qout: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0) ); END counter10; --*************************** ARCHITECTURE demux4_behave OF counter10 IS SIGNAL RST:STD_LOGIC; SIGNAL QN:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN proceSS(CP,RST) BEGIN IF RST='1'THEN QN="0000"; ELSIF CP'EVENT AND CP='1'THEN QN=QN+1; END IF; END PROCESS; RST='1'WHEN QN="10" ELSE '0'; Qout=QN; END demux4_behave;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity division5 is port (clk: in std_logic; out1: out std_logic); end division5; architecture Behavioral of division5 is signal division2,division4 :std_logic; signal temp1,temp2:integer range 0 to 10; begin p1:process(clk) begin if rising_edge(clk) then temp1=temp1+1; if temp1=2 then division2='1'; elsif temp1=4 then division2='0'; temp1=0; end if; end if; end process p1; p2:process(clk) begin if clk'event and clk='0' then temp2=temp2+1; if temp2=2 then division4='1'; elsif temp2=4 then division4='0'; temp2=0; end if; end if; end process p2; p3:process(division2,division4) begin out1=division2 or division4; end process p3; end Behavioral;