tag 标签: jitter

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  • 热度 8
    2022-6-21 08:41
    6891 次阅读|
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    谈谈晶振的相位噪声(Noise)和抖动(jitter)
    晶振是个大家族,除了SPXO外,更有压控晶体振荡器(VCXO)、温补晶体振荡器(TCXO)、恒温晶体振荡器(OCXO),以及数字补偿晶体振荡器(MCXO或DTCXO),每种类型都有独特的性能,例如相位噪声和抖动(jitter)这两个指标。 什么是相位噪声和抖动? 简单讲,抖动(jitter)是某一事件的时程与理想时程的时间偏差,单位以fs(微微秒、飞秒,即10-15秒),或者ps(皮秒,1ps = 1000fs = 10-12秒)表示。 如果用仪器测量,呈现出的是信号的频域特性,称作“相位噪声(Phase Noise)”。本质上,这两者是一样的,只是表述方式不同而已。 (1)抖动 抖动分确定性抖动(Deterministic jitter,DJ)和随机性抖动(Random jitter,RJ)两种。DJ通常幅度有限,以单位时间表示;RJ为高斯分布,以RMS均方根值表示,RMS Jitter值大小与振荡输出频率成反比。 晶体振荡器的RMS Jitter值与输出频率成反比 晶振的抖动通常由噪声引起,并导致频率不稳定。对于精密电子仪器、无线电定位、高速目标跟踪和宇航通信等应用领域,选择低噪声晶振十分重要。 (2)相位噪声 相位噪声(Phase Noise)是抖动在测量仪器上的表现,通常定义为一个振荡器在某一偏移频率fm处1Hz宽带内的单边信号功率和信号总功率比值,单位是dBc/Hz,通常表示为dBc/Hz@fm。 若没有相位噪声,振荡器的整个功率都集中在f0(10MHz为例),功率频谱就是一条以f0为中心的直线,且信号为纯正的正弦波。但是任何信号都有不稳定性,从而产生了边带sideband。 相位噪声的来源主要有三方面: (1)晶体品质Q值。高频晶体有很高的近载波相位噪声(Close-in Phase Noise), 因为他们有低的Q值和更宽的边带。 (2)晶体外围电路:包括包括IC、RC元件、引脚等。 (3)信号输出(白噪声)。 高速系统对晶振相位噪声的要求 在通信网络、无线传输、ATM和SONET等高速系统中,时钟或振荡器波形的时序误差会限制一个数字I/O接口的最大速率。不仅如此,它还会导致通信链路的误码率增大,甚至限制A/D转换器的动态范围。有资料表明,在3GHz以上的系统中,时间抖动(jitter)会导致码间干扰(ISI),造成传输误码率上升,这就要求晶振选型必须满足严格的抖动指标。 如果需要设备即开即用,就必须选用VCXO或温补晶振;如果要求稳定度在0.5ppm以上,则需选择数字温补晶振(MCXO)。模拟温补晶振适用于稳定度要求在5ppm~0.5ppm之间的需求。VCXO只适合于稳定度要求在5ppm以下的产品。在不需要即开即用的环境下,如果需要信号稳定度超过0.1ppm的,可选用OCXO。 面向高速通讯应用的高频低噪声晶体振荡器 一般来说,晶体振荡器的相位噪声在远离中心频率的频率下有所改善。TCXO和OCXO振荡器以及其它利用基波或谐波方式的晶体振荡器具有最好的相位噪声性能。采用锁相环合成器产生输出频率的振荡器比采用非锁相环技术的振荡器一般呈现较差的相位噪声性能。例如,对于需要低噪声、稳定和精确时钟源的工业级设备(比如收发器模块或数据中心),可选择150fs小型塑封石英PLL振荡器;而通讯、导航、雷达应用领域的要求会有更高如50fs,这需要将100MHz以上基波起振的高频石英晶体单元与噪音特性优越的振荡IC相组合。
  • 热度 18
    2015-1-22 18:15
    2366 次阅读|
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    All data streams experience jitter, some of which is statistically random, so that means we must characterize it with statistics. In jitter analysis, random jitter (RJ) is often described as having a Gaussian distribution.   RJ is typically quantified as an rms value equal to σ of the Gaussian formula. Since Gaussian distributions are unbounded, a peak-to-peak value of RJ requires a measure of probability of bit errors, or BER (bit error ratio). For a typical specification of BER = 10 -12 , (1 error for every 10 12 bits) the peak-to-peak value of RJ is closely approximated by 14σ, where σ is one standard deviation.   Figure 1 shows a plot of the familiar Gaussian distribution. We are often concerned with probability in any given area of this bell curve. Table 1 shows the probability of events occurring in the peak and tail regions for different spans of σ.   Figure 1. Gaussian distribution.   Table 1. Probability of peak and tail areas vs. number of σ.   At ±6σ, we see that the probability of the tails is about two in a billion. For ±7σ, the probability of the tails is about 2.6 in a trillion, which is roughly how we came to use 14σ to bound RJ at BER = 10 -12 . Even though we frequently talk about probabilities of less than one in a trillion, few people actually have an intuitive grasp of such large/small numbers. I came across a very interesting example to illustrate Gaussian distributions using the distribution of height in American men.   The US has approximately 300 million people, out of whom approximately 100 million are non-acromegalic adult men (i.e., no abnormal pituitary problems affecting their height). The mean height of men in the US is about 5'9" with a standard deviation of 3". Knowing how Gaussian distributions work, we can estimate how many men are in each height bracket, shown below in Table 2.   Table 2. The probability of the height of men.   We see that about 68 million men are within ±1σ of the mean, which is between 5'6" and 6' tall. We refer to this range as average height. We think of men between 6' and 6'3" as being relatively tall, but there is still a large population of them, about 13.6 million or 13.6 percent. The numbers drop off very quickly for increasing heights, as expected.   What is interesting is that Gaussian statistics tell us that there should be no men in the US who are above 7'3" tall. But, many sports fans can immediately point out that Yao Ming is 7'6". Someone of Yao Ming's height is statistically unlikely in the normal height distribution of American men.   So, why is Yao Ming Chinese? Because the US does not have enough adult men to realize someone who is greater than 6σ in height! Instead, Yao Ming was born in China, where the current population of adult men is about 500 million, which is five times more likely to grow a 6σ person. Furthermore, the mean height of men in China is approximately 5'7", which makes Yao Ming's stature even more statistically rare!   Yao Ming, basketball player for the Houston Rockets (retired).   Many readers will quickly point out that India also has a population comparable to China's. Is there at least one Indian man who is 6σ above the mean in height? The answer is a resounding yes! Sunil Chaudhary currently claims to be the tallest living man in India at a height of 7’6", a number that neatly fits into our understanding of 6σ in Gaussian distributions.   So, in jitter analysis, when we are looking for that less-than-one-in-a-trillion event that determines our BER compliance, or when we test for violations with a PRBS31 (2 31 −1) pattern -- 2.4 billion bits long -- I like to tell people I'm searching for the "Yao Ming of jitter."   Daniel Chow
  • 热度 18
    2015-1-22 18:14
    1902 次阅读|
    0 个评论
    All data streams experience jitter, some of which is statistically random, meaning that we must characterize it with statistics. In jitter analysis, random jitter (RJ) is often described as having a Gaussian distribution.   RJ is typically quantified as an rms value equal to σ of the Gaussian formula. Since Gaussian distributions are unbounded, a peak-to-peak value of RJ requires a measure of probability of bit errors, or BER (bit error ratio). For a typical specification of BER = 10 -12 , (1 error for every 10 12 bits) the peak-to-peak value of RJ is closely approximated by 14σ, where σ is one standard deviation.   Daniel Chow   Figure 1 shows a plot of the familiar Gaussian distribution. We are often concerned with probability in any given area of this bell curve. Table 1 shows the probability of events occurring in the peak and tail regions for different spans of σ.   Figure 1. Gaussian distribution.   Table 1. Probability of peak and tail areas vs. number of σ.   At ±6σ, we see that the probability of the tails is about two in a billion. For ±7σ, the probability of the tails is about 2.6 in a trillion, which is roughly how we came to use 14σ to bound RJ at BER = 10 -12 . Even though we frequently talk about probabilities of less than one in a trillion, few people actually have an intuitive grasp of such large/small numbers. I came across a very interesting example to illustrate Gaussian distributions using the distribution of height in American men.   The US has approximately 300 million people, out of whom approximately 100 million are non-acromegalic adult men (i.e., no abnormal pituitary problems affecting their height). The mean height of men in the US is about 5'9" with a standard deviation of 3". Knowing how Gaussian distributions work, we can estimate how many men are in each height bracket, shown below in Table 2.   Table 2. The probability of the height of men.   We see that about 68 million men are within ±1σ of the mean, which is between 5'6" and 6' tall. We refer to this range as average height. We think of men between 6' and 6'3" as being relatively tall, but there is still a large population of them, about 13.6 million or 13.6 percent. The numbers drop off very quickly for increasing heights, as expected.   What is interesting is that Gaussian statistics tell us that there should be no men in the US who are above 7'3" tall. But, many sports fans can immediately point out that Yao Ming is 7'6". Someone of Yao Ming's height is statistically unlikely in the normal height distribution of American men.   So, why is Yao Ming Chinese? Because the US does not have enough adult men to realize someone who is greater than 6σ in height! Instead, Yao Ming was born in China, where the current population of adult men is about 500 million, which is five times more likely to grow a 6σ person. Furthermore, the mean height of men in China is approximately 5'7", which makes Yao Ming's stature even more statistically rare!   Yao Ming, basketball player for the Houston Rockets (retired).   Many readers will quickly point out that India also has a population comparable to China's. Is there at least one Indian man who is 6σ above the mean in height? The answer is a resounding yes! Sunil Chaudhary currently claims to be the tallest living man in India at a height of 7’6", a number that neatly fits into our understanding of 6σ in Gaussian distributions.   So, in jitter analysis, when we are looking for that less-than-one-in-a-trillion event that determines our BER compliance, or when we test for violations with a PRBS31 (2 31 −1) pattern -- 2.4 billion bits long -- I like to tell people I'm searching for the "Yao Ming of jitter."
  • 热度 19
    2015-1-4 09:05
    997 次阅读|
    0 个评论
    系统时序设计中对时钟信号的要求是非常严格的,因为我们所有的时序计算都是以恒定的时钟信号为基准。但实际中时钟信号往往不可能总是那么完美,会出现抖动(Jitter)和偏移(Skew)问题。 所谓抖动(jitter),就是指两个时钟周期之间存在的差值,这个误差是在时钟发生器内部产生的,和晶振或者PLL内部电路有关,布线对其没有影响。除此之外,还有一种由于周期内信号的占空比发生变化而引起的抖动,称之为半周期抖动。总的来说,jitter可以认为在时钟信号本身在传输过程中的一些偶然和不定的变化之总和。0Y:L7J 时钟偏移(skew)是指同样的时钟产生的多个子时钟信号之间的延时差异。它表现的形式是多种多样的,既包含了时钟驱动器的多个输出之间的偏移,也包含了由于PCB走线误差造成的接收端和驱动端时钟信号之间的偏移。 信号完整性对时序的影响,比如串扰会影响微带线表传播延迟(带状线,内层);反射会造成数据信号在逻辑门限附近波动,从而影响最大/最小飞行时间;时钟走线的干扰会造成一定的时钟偏移。有些误差或不确定因素是仿真中无法预见的,设计者只有通过周密的思考和实际经验的积累来逐步提高系统设计的水平。 Clock skew 和Clock jitter 是影响时钟信号稳定性的主要因素。很多书里都从不同角度里对它们进行了解释。 其中“透视”一书给出的解释最为本质: Clock Skew: The spatial variation in arrival time of a clock transition on an integrated circuit; Clock jitter: The temporal vatiation of the clock period at a given point on the chip; 简言之,skew通常是时钟相位上的不确定,而jitter是指时钟频率上的不确定(uncertainty)。造成skew和jitter 的原因很多。由于时钟源到达不同寄存器所经历路径的驱动和负载的不同,时钟边沿的位置有所差异,因此就带来了 skew。而由于晶振本身稳定性,电源以及温度变化等原因造成了时钟频率的变化,就是jitter。 skew和jitter对电路的影响可以用一个简单的时间模型来解释。假设下图中t(c-q)代表寄存器的最大输出延迟, t(c-q, cd)表示最大输出延时;t(su)和t(hold)分别代表寄存器的setup, hold time(暂不考虑p.v.t)差异;t(logic) 和t(logic, cd)分别表示最大的组合逻辑传输延迟和最小组合逻辑传输延迟;   在不考虑skew和jitter的情况下,及t(clk1)和t(clk2)同频同相时,时钟周期T和t(hold)需要满足  T  t(c-q) + t(logic) + t(su)  t(hold)  t(c-q, cd) + t(logic, cd) 这样才能保证电路的功能正常,且避免竞争的发生。如果考虑CLK2比CLK1晚t1的相位,及skew=t1。 则 t(hold)  t(c-q, cd) + t(logic, cd) - t1 这意味着电路由更大的倾向发生hold time violation;如果考虑CLK1比CLK2晚t2的相位,及skew=-t2, 则 T  t(c-q) + t(logic) + t(su) + t2 这意味着电路的性能下降了,但由于R2的hold time始终满足,所以不会有竞争的麻烦存在。clock jitter 始终是对性能造成负面的影响,一般设计中都需要专门留取10%左右的margin来保证。 clock uncertainty = clock jitter + clock skew. jitter 是 由时钟源产生的抖动。skew是时钟树不平衡引起的到达两个寄存器的延迟差。在cts之后,skew由工具算出,因此sta的时候clock uncertainty 可以设一个比较小的值。另外做hold check的时候因为检查的是同一个时钟沿,因此没有jitter只有skew.   slack + 满足时序 -不满足 设计是否满足时序的一个称谓
  • 热度 26
    2014-10-16 16:28
    1587 次阅读|
    0 个评论
    The issue of jitter and how to deal with it in all its forms--clock, phase, and timing, among others--is a constant in an embedded developer's life. Now, as the world has become increasingly connected, network and packet jitter complicate the developer’s life.   But this is not a problem that is faced only by developers of high performance communications systems. It is occurring in our homes and offices with the growing number of connected devices that often occupy the same confined transmission space.   The problems it causes have recently for me become personal. I now share my home and my home office with a variety of connected devices, both wired and wireless: USB mouse devices, a wirelessly connected printer, a wirelessly connected laptop and desktop computer, a Voice Over IP phone, wireless handsets for my home phone, an ebook device that has content delivered to it wirelessly, an MP3 player with a radio receiver and, oh yes, a mobile phone. And as the Internet of Things phenomenon grows, I am sure there will be still more, whether I need them or not.   As I know from personal experience, the various jitter problems from the interactions of these signals can cause a display on a device to flicker, introduce clicks and other undesired effects into audio signals, and cause loss of transmitted data between network devices. Often the only way to solve the problem without returning the unit is by keeping some physical separation between the devices, often putting the offending systems in separate rooms.   According to the text books, jitter is a measure of the deviation of any communications signal from true periodicity as specified in a design, often in relation to a reference clock source. Jitter manifests itself in many forms, such as in the frequency of successive pulses, the amplitude of the signal, or in the phase of the signal.   Jitter has always been a significant and undesirable characteristic of any design that makes use of high data rate workhorse communications links that embedded developers are familiar with: USB, PCI-e, SATA, and OC-48, among others. But now many other systems - such as mobile phones, wearable medical devices, Zigbee, and other wireless network devices in the home - are increasingly susceptible to a variety of jitter problems.   In a world where many of these connected devices, both wired and wireless, co-exist in the same environment, the problems become even more difficult, with jitter introduced into a previously functioning device by electromagnetic interference (EMI) and crosstalk with carriers of other signals.   And in an increasingly connected Internet of Things world such problems, such problems can be particularly hard to pin down and specify in a design. Fortunately, there are a wide range of techniques and tools available.   Much more work remains to be done, both in applying existing tools and techniques to this problem as well as in developing new ones. I look forward to hearing from you about the methods and building blocks you use in your designs. I also look forward to conferences, where a whole new set of methods and techniques to deal with signal jitter in all its forms will be discussed.   Personally, I hope the new and better tools and techniques arrive quickly. I am adding connected - and noisy - mobile and wireless devices as fast as I am convinced they will be useful to me. But I am running out of rooms and tricks to keep them operating as they should.
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    Abstract:TheThermalNoiseCalculator(TNC)aidsintheanalysisofthermalnoisefoundinresistorsandothernoisesources.TheprogramisforusewithanHP®50gcalculatororfreePCemulator.Maxim>DesignSupport>AppNotes>A/DandD/AConversion/SamplingCircuits>APP5059Maxim>DesignSupport>AppNotes>AmplifierandComparatorCircuits>APP5059Maxim>DesignSupport>AppNotes>DigitalPotentiometers>APP5059Keywords:thermalnoise,noisevoltage,whitespectraldensity,Johnsonresistance,temperature,1/fcornerfrequency,calculators,analogcircuitdesign,HP50gprograms,designtool,circuitanalysis,signaltestmeasurement,bandwidth,clock,jitter,analogreferredAug23,2011APPLICATIONNOTE5059ThermalNoiseCalculatorTutorialBy:BillLaumeister,StrategicApplicationsEngineerAbstract:TheThermalNoiseCalculator(TNC……
  • 所需E币: 3
    时间: 2019-12-24 22:04
    大小: 289.47KB
    上传者: 16245458_qq.com
    Abstract:Analog-to-digitalconverters(ADCs)representthelinkbetweenanaloganddigitalworldsinreceivers,testequipmentandotherelectronicdevices.AsoutlinedinPart1ofthisarticleseries,anumberofkeydynamicparametersprovideanaccuratecorrelationofthedynamicperformancetobeexpectedfromagivenADC.Part2ofthisarticleseriescoverssomeofthesetupconfigurations,equipmentrecommendationsandmeasurementproceduresfortestingthedynamicspecificationsofhigh-speedADCs.Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP729Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP729Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP729Keywords:analogtodigitalconverters,ADCs,high-speedADC,SNR,SINAD,ENOB,THD,SFDR,two-toneIMD,multi-toneIMD,clockjitter,FFT,spectrum,windowfunctions,spectralleakage,frequencybin,bins,coherentsampling,hanning,hamming,flattopJul22,2002TUTORIAL729DynamicTestingofHigh-SpeedADCs,Part2Jul22,2002Abstract:Analog-to-digital……
  • 所需E币: 5
    时间: 2019-12-24 22:05
    大小: 56.82KB
    上传者: 238112554_qq
    Abstract:ThisapplicationnoteclarifiestheoperationandapplicationsoftheMaximJitterCalculatorprovidedaspartoftheADCdesigntools.ThisdocumentassumesthatthereaderhasabasicunderstandingofterminologyandconceptsrelatedtoADCs(Formoreinformation,seeapplicationnote641,"ADCandDACGlossary.")Maxim>AppNotes>A/DandD/AConversion/SamplingCircuitsHigh-SpeedSignalProcessingKeywords:ADCApertureJitterCalculatorSNRSep08,2009APPLICATIONNOTE4466ApertureJitterCalculatorforADCsAbstract:ThisapplicationnoteclarifiestheoperationandapplicationsoftheMaximJitterCalculatorprovidedaspartoftheADCdesigntools.ThisdocumentassumesthatthereaderhasabasicunderstandingofterminologyandconceptsrelatedtoADCs(Formoreinformation,seeapplicationnote641,"ADCandDACGlossary.")IntroductionTheMaximJitterCalculatorisintendedforusewithADCsthathaveaclock-based,input-samplingscheme(sample/track-and-hold(T/H)front-end)foracquisitionofdynamicinputsignals……
  • 所需E币: 4
    时间: 2019-12-24 22:05
    大小: 72.09KB
    上传者: 微风DS
    Abstract:Interleavingmultipleanalog-to-digitalconverters(ADCs)isusuallyperformedwiththeintenttoincreaseaconverterseffectivesamplerate,especiallyiftherearenooronlyfewoff-the-shelfADCsavailablethatfulfillthedesiredsample,linearityandACrequirementsofsuchapplications.However,time-interleavingdataconvertersisnotaneasytask,becauseevenwithperfectlylinearcomponents,gain/offsetmismatchesandtimingerrorscancauseundesiredspursintheoutputspectrum.Thefollowingarticleprovidesvaluableinsightintothetheoreticalapproachoftime-interleavedanalog-to-digitalconvertersandthekindofroadblocks(andhowtocompensateforthem)adesignerusuallyencounterswhenbuildingatime-interleavedsystem.Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200……
  • 所需E币: 3
    时间: 2019-12-24 22:05
    大小: 131.19KB
    上传者: 978461154_qq
    Abstract:High-speedapplicationsusingultra-fastdataconvertersintheirdesignoftenrequireanextremelycleanclocksignaltomakesureanexternalclocksourcedoesnotcontributeundesirednoisetotheoveraldynamicperformanceofthesystem.Itisthereforecrucialtoselectsuitablesystemcomponents,whichhelpgeneratealowphase-jitterclock.Thefollowingapplicationnoteservesasavaluableguideforselectingtheappropriatecomponentstodesignalow-phasenoisePLL-basedclockgenerator,suitableforultra-fastdataconverters.Maxim>AppNotes>A/DandD/ACONVERSION/SAMPLINGCIRCUITSHIGH-SPEEDSIGNALPROCESSINGKeywords:high-speedADCs,high-speedanalogtodigitalconverter,PLL,VCO,phase-lockedloop,voltage-Nov20,2001controlledoscillator,lowphasenoise,lowphasejitter,clockjitter,crystaloscillator,noise,SNR,spuriouscomponents,analogdigital,dataconvertersAPPLICATIONNOTE800DesignaLow-JitterClockforHigh-SpeedDataConvertersAbstract:High-speedapplicationsusingultra-fastdataconvertersintheirdesignoftenrequireanextremelycleanclocksignaltomakesureanexternalclocksourcedoesnotcontributeundesirednoisetotheoveraldynamicperformanceofthesystem.Itisthereforecrucialtoselectsuitablesystemcomponents,whichhelpgene……
  • 所需E币: 4
    时间: 2019-12-24 21:52
    大小: 69.76KB
    上传者: quw431979_163.com
    Abstract:Engineersoftenwishthatradiosusceptibility(RS)orradioimmunitycouldbecuredwithanantibiotic,avaccine,orsomeformofcure-all.Unfortunately,solvingtheRSproblemisnotthateasy.Indeed,thelawsofphysicsapply.InthisarticlewediscusssourcesofRS.Wealsooffertipsandhintstoprotectsystems,powersupplies,printedcircuitboards(PCBs),andelectroniccomponentsfromradiofrequencyinterference.Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP5065Maxim>DesignSupport>TechnicalDocuments>Tutorials>AmplifierandComparatorCircuits>APP5065Maxim>DesignSupport>TechnicalDocuments>Tutorials>CommunicationsCircuits>APP5065Keywords:radiosusceptibility,powersupplies,grounding,printedcircuitboard,electroniccomponents,radiofrequencyinterference,radioimmunity,electromagneticfield,EMI,RFI,jittertransitions,IntegratedfilterIC,inputoutputports,powerline,RSJan03,2012TUTORIAL5065RadioSusceptibility―CurewithAntibiotic,Vaccine,ortheLawsofPhysics……
  • 所需E币: 4
    时间: 2019-12-24 20:20
    大小: 528.73KB
    上传者: 238112554_qq
    eSATA的测量方法MeasurementmethodologyeSATARev1.21PHYtestingmethodology……
  • 所需E币: 4
    时间: 2019-12-24 19:26
    大小: 289.47KB
    上传者: wsu_w_hotmail.com
    摘要:模拟-数字转换器(ADC)的代表在接收器,测试设备及其他电子设备的模拟和数字世界之间的联系。正如在本系列文章的第1部分所述,一些关键的动态参数,提供准确的相关性的动态性能,可以从一个给定的ADC预期。本系列文章的第二部分包括一些安装配置,设备的建议和高速ADC的动态规格测试测量程序。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP729Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP729Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP729Keywords:analogtodigitalconverters,ADCs,high-speedADC,SNR,SINAD,ENOB,THD,SFDR,two-toneIMD,multi-toneIMD,clockjitter,FFT,spectrum,windowfunctions,spectralleakage,frequencybin,bins,coherentsampling,hanning,hamming,flattopJul22,2002TUTORIAL729DynamicTestingofHigh-SpeedADCs,Part2Jul22,2002Abstract:Analog-to-digital……
  • 所需E币: 5
    时间: 2019-12-24 19:25
    大小: 72.09KB
    上传者: 16245458_qq.com
    摘要:交错多个模拟-数字转换器(ADC)通常采用增加一个转换器,有效样本率的意图,尤其是如果有没有或只有很少可用的现成的ADC完成所需的样品,线性交流等应用的要求。然而,时间交错的数据转换器是不是一件容易的事,因为即使有完美的线性元件,增益/偏移不匹配和时序错误可能会导致在输出频谱中意外马刺。时间交错的模拟-数字转换器和路障(以及如何补偿他们)的理论方法,设计师通常会建立一个时间交错系统时遇到下面的文章提供了宝贵的见解。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200……
  • 所需E币: 4
    时间: 2019-12-24 19:21
    大小: 289.47KB
    上传者: wsu_w_hotmail.com
    摘要:模拟-数字转换器(ADC)的代表在接收器,测试设备及其他电子设备的模拟和数字世界之间的联系。正如在本系列文章的第1部分所述,一些关键的动态参数,提供准确的相关性的动态性能,可以从一个给定的ADC预期。本系列文章的第二部分包括一些安装配置,设备的建议和高速ADC的动态规格测试测量程序。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP729Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP729Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP729Keywords:analogtodigitalconverters,ADCs,high-speedADC,SNR,SINAD,ENOB,THD,SFDR,two-toneIMD,multi-toneIMD,clockjitter,FFT,spectrum,windowfunctions,spectralleakage,frequencybin,bins,coherentsampling,hanning,hamming,flattopJul22,2002TUTORIAL729DynamicTestingofHigh-SpeedADCs,Part2Jul22,2002Abstract:Analog-to-digital……
  • 所需E币: 4
    时间: 2019-12-24 19:21
    大小: 72.09KB
    上传者: 978461154_qq
    摘要:交错多个模拟-数字转换器(ADC)通常采用增加一个转换器,有效样本率的意图,尤其是如果有没有或只有很少可用的现成的ADC完成所需的样品,线性交流等应用的要求。然而,时间交错的数据转换器是不是一件容易的事,因为即使有完美的线性元件,增益/偏移不匹配和时序错误可能会导致在输出频谱中意外马刺。时间交错的模拟-数字转换器和路障(以及如何补偿他们)的理论方法,设计师通常会建立一个时间交错系统时遇到下面的文章提供了宝贵的见解。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200……
  • 所需E币: 4
    时间: 2019-12-24 18:18
    大小: 72KB
    上传者: 二不过三
    摘要:数位计算器(ENOB),艾滋病在数据转换器应用电路的设计和分析的有效。它计算的ENOB,SINAD,分辨率,信号带宽,过采样率,DNL的,时钟抖动,模拟噪声和THD。该计算器可用于惠普®50克计算器或免费的PC模拟器。Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP5061Maxim>DesignSupport>TechnicalDocuments>Tutorials>DigitalPotentiometers>APP5061Maxim>DesignSupport>TechnicalDocuments>Tutorials>MeasurementCircuits>APP5061Keywords:EffectiveNumberBits,Calculator,ENOB,DataConverter,SINAD,Resolution,Signal,OversampleRates,DNL,Clock,Jitter,AnalogNoise,THD,ADC,DAC,AnalogDesign,DigitalAccuracy,HP50g,INL,TotalHarmonicDistortionAug09,2011TUTORIAL5061EffectiveNumberofBitsCalculatorTutorialBy:BillLaumeister,StrategicApplicationsEngineerAbstract:TheEffectiv……