抖动对ADC性能产生的影响是由输入频率而不是采样率产生。时钟源的选择由应用需求决定。尽量用ADC评估板对时钟源进行测试，而不是相信时钟厂商的说法。 advertisement Understanding the Effect of Clock Jitter on High Speed ADCs Design Note 1013 Derek Redmayne (LTC Applications Engineer), Eric Trelewicz (LTC Applications Manager) and Alison Smith (High Speed ADC Product Marketing Engineer) Digitizing high speed signals to a high resolution requires tone, or a narrow band, with equivalent power at 1MHz. careful selection of a clock that will not compromise the There are various contributors to jitter in any scenario, sampling performance of the Analog to Digital Converter extending from the oscillator to any frequency dividers, (ADC). In this article we h……