tag 标签: level

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    2021-7-6 15:40
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    1.Report Clock Networks report_clock_networks -name {network_1} 2.分析设计中逻辑级数的分布 report_design_analysis -logic_level_distribution -logic_level_dist_paths 5000 -name design_analysis_prePlace 3.筛选"clk"时钟域逻辑级数在 之间的c条路径 report_timing -name longPaths -of_objects -max_paths c = a && LOGIC_LEVELS<= b }] 4.扇出分析 扇出大于a的b条路经 report_high_fanout_nets -fanout_greater_than a -max_nets b 5. freq & level 125M以下:13级 125-250: 6级 250-350: 5级 350-400: 4级 400以上: 3级 6. ERROR : Finished Running Vector-less Activity Propagation 604 INFO: Applying IDT optimizations ... 605 INFO: Applying ODC optimizations ... 606 ERROR: Unhandled exception occurred during power optimization. 607 ERROR: Power Optimization encountered an error. 解决方法:opt_design -directive NoBramPowerOpt
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