标签: Package

Over the past decade the embedded world has undergone tremendous change. With the advent of mobile phones, smart lifestyle gadget like wearables, health and wellness devices, on the consumer front, users are demanding smaller and thinner gadgets. This has lead in turn to designs that increasingly need efficient memory architectures such as high memory capacity and high performance in small area and multiple bus issues that call for high scalability.  The designs demand compact and more densely populated electronic assemblies. Package on package (PoP) is one of the techniques to address the demand for compact assemblies. PoP is a stacked packaging method to have two ball grid array (BGA) packages mounted one above the other with a standard interface to route signals between them. The most widely used integration components for stacking are the processor and memory. The combination of RAM Flash memory in single chip BGA solution is also available, which allows a much higher component density on smaller form factor PCB design through the PoP assembly.   Stacking memory is one way to achieve the dual goals for enhanced functionality and greater packaging density of a product. It is fast becoming a promising solution, offering high integration that leads to product miniaturization. Mobile applications can benefit from the combination of this stacked package, offering small footprint and minimal PCB space. Other portable electronic products such as •      mobile phones (baseband or applications processor plus combo memory), •       digital cameras (image processor plus memory), •       PDAs, portable media players (audio/graphics processor plus memory), gaming and others also benefit from this design approach. Benefits of PoP Technology Using PoP technology in a design offers many advantages. The most obvious is the reduction in the PCB size or the small footprint of the PCB. Using PoP technology also ensures a reduction in the no. of layers of the PCB as the connection lines between the processor and the memory are minimized. This also improves signal integrity on the board by minimizing trace length between different interoperating parts, such as controller and memory. The direct interconnections between the circuit yields reduced propagation delay, noise and cross-talk.  Using PoP technology also makes for easy memory scalability on the hardware. This is because most of the memory modules for PoP design come in multi-chip packages (eg: Flash + DDR). Hence, both the Flash and DDR memory can be upgraded by replacing the single PoP memory package. And finally, there is the reduction in BoM cost achieve as a result of elimination of termination discretes on the PCB. The ARM advantage PoP technology is most popularly being used with ARM chipsets. Texas Instruments was one of the first semiconductor companies that adopted this technology. This is now being followed by other silicon vendors like Freescale etc. ARM chipsets are known for low power and are popular for small footprint, portable applications. The low power ensures less thermal radiation to the memory; when it is placed over the processor in the PoP technology. In comparison, Intel SoCs and other DSP are high power and have high thermal radiation. Therefore, there is a possibility of the memory to stall during operation, if the PoP technology concept is used for these chipsets.   An important point to note for product developers is that assembly of PoP PCBs requires special skillset and the need to follow a defined assembly process. The PCB manufacturer should follow the required methodology to ensure minimal yield issues for a successful implementation to take advantage of the benefits of such a design.   Contributed By, S Vijay Bharat, Associate Vice President - Hardware Design, Mistral Solutions

Well these are the commonly used smd IC footprint that I have collected so far... SMD  Package Footprint/Dimension/Datasheet     Resistor/Capacitor   diagram taken from Wiki 0603   Size: 1.5 mm × 0.8 mm (0.06" × 0.03")   0805   Size: 2.0 mm × 1.3 mm (0.08" × 0.05") 1206   Size: 3.0 mm × 1.5 mm (0.12" × 0.06") 1812   Size: 4.6 mm × 3.0 mm (0.18" × 0.12") 2010   Size: 5.2 mm × 2.6 mm (0.20" × 0.10") 2512   Size: 6.5 mm × 3.2 mm (0.25" × 0.12") Resistor array smd 4P2R (L x W2) Size 0201 4P2R (1.4 x 0.6mm) Size 0402 4P2R (2.0 x 1.0mm) Size 0603 4P2R (3.2 x 1.6mm) Size 0805 4P2R (5.08 x 2.2mm) YC164 (Convex Terminal type), TC164 (Concave Terminal type) smd footprint size taken from Panasonic datasheet. footprint layout size taken from YAGEO datasheet.     Package typically for diode   SMA, D-64 SMB, 403a-03 SMC SMF, DO219-AB SC79     PLCC   PLCC-2 (for LED) plcc-2.pdf     SOT   SOT23-3 sot23-3 21-0051.PDF sot23_philips.pdf SOT23-5 sot23-5 21-0057.PDF SOT23-6 sot23-6 21-0058.PDF SOT23-8 sot23-8 21-0078.PDF SOT143-4 sot143-4 21-0052.PDF SOT143b   SOT323 SOT363 SOT416 SOT666 SOD123f SOD323 SOD523 SOD882 SOD323 SOD123 SOD523 SMA SMB SMC MELF MiniMELF X1-DFN1006-2 X2-DFN1006-2      From: http://www.siongboon.com/projects/2005-09-07_home_pcb_fabrication/footprint/