原创 Receiver path (一) - PMA

2009-11-13 13:22 3225 8 8 分类: FPGA/CPLD

接收端PMA,与发送端相对应,大致分三个模块,Deserializer、CDR以及RX buffer。如下所示:


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我们来看RX buffer,如下所示:


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Deserializer没什么好说的,CDR说明如下:


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        The CDR has two operating modes, lock-to-reference (LTR) and lock-to-data (LTD).  In LTR mode, the phase frequency detector tracks the input reference clock.  This mode is used to train the CDR, for example when first bringing up the transceiver or when the CDR loses lock with the incoming data.  In LTD mode, the detector tracks the incoming data.  This mode is used during normal operation of the receiver.



        To select between the modes, the controller circuit itself has two modes, automatic and manual. 


 


CDR有两种工作模式,前面说了这两种工作模式之间的切换控制有两种方式,分别是自动、手动。下面分别介绍,先说自动控制方式:


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        In automatic locking mode, the controller switches from LTR to LTD modes whenever the phases of the reference clock and the CDR output clock are within 0.08 UI of each other AND the two clocks are within a user-defined PPM frequency threshold of each other. This slide shows the supported PPM threshold values.  If the CDR falls out of the PPM frequency threshold of the reference clock, then the CDR controller switches the CDR back to LTR mode. Thus, if your system experiences frequency drift between the link endpoints, the CDR falls out of lock. 



        A PPM value should be chosen depending on how much “play” you want in your link.   Choose a smaller number if your require tight frequency coupled endpoints, for example in the case where you have a fully synchronous system with both endpoint clocks derived from the same oscillator.   Choose a larger number if your endpoint clocks are not fully synchronous but within a certain PPM specification. Remember that each time you switch back to LTR mode, the CDR is no longer tracking the data and received data could be lost or corrupted.  So you want to match this value to what you want to support in your system.



        To monitor the status of the controller, the rx_freqlocked signal shows a high when in LTR mode and a low when in LTD mode.  When in LTR mode, you application controller can start receiving data.


 


再说手动控制方式,如下所示:


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Manual CDR controller operation lets you design your own custom logic to control switchover.  This may be required, for example, if your spec requires faster CDR switching than what is provided by the automatic circuitry.  To operate the CDR controller in manual mode, enable the rx_locktorefclk and rx_locktodata control signals.  The rx_locktorefclk signal forces the CDR into LTR mode and the rx_locktodata forces the CDR into LTD mode.  The table shows the relationship and priority of the two control signals.



To monitor the CDR, you should enable the rx_pll_locked flag.  A high on this signal indicates the CDR is locked to the reference clock.  Upon seeing this, your logic could initiate a switch to LTD mode.

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