原创 Receiver path （一） - PCS

Receiver 路径上的PCS包含的模块较多，根据发送端的设置设置接收端的功能模块，另外对于有些模块之间的选用是互斥的，比如Rate match FIFO和Word aligner，PCS的功能框图如下所示：

Word aligner以及Rate match FIFO有点复杂，详细的内容可以参考handbook，这里只给出功能框图：

而8B/10B解码和字节解串模块对于与发送端的8B/10B编码和字节串化，这里也只给出功能框图：

重点推荐的模块是byte ordering，根据在发送端最低字节（LSB）发送特定k码，接收端该模块来探测并调整确定正确的接收数据字节顺序，功能框图如下所示：

        The byte ordering block is used to ensure the byte transmitted in the LSByte position of the data word remains in that position at the output of the receiver.   For example, what was transmitted in byte0 might end up any other byte position after the receiver comes out of reset.  The byte ordering block restores that original byte positioning.  To control this block there is an optional signal rx_enabyteord.  A rising edge on this signal triggers the byte ordering circuitry.  To check whether ordering is completed, you can enable and monitor the rx_byteordalignstatus flag is driven high whenever a byte ordering is successful.  This is true even if byte ordering block didn’t actually have to do any realignment.

        To perform byte ordering, the designer must define a user-programmable byte ordering pattern and send this pattern in the LSByte position.  When the byte ordering block finds the pattern, it inserts user-programmable pad characters to push the byte ordering pattern into the LSByte.  This ordering pattern could be a previously defined start of packet symbol or a special character used specifically to perform byte ordering.

        The rate matching FIFO must be disabled to do byte ordering as inserting and deleting skip patterns would throw the byte ordering off again.

        This table shows the supported settings for using the byte ordering block in single-width mode.  As you can see, there are essentially two configurations supported.  Both require the FPGA-transceiver interface being set to 16 bits.  The first configuration is with 8B/10B decoding disabled and the word aligner set to manual alignment.  In this configuration, the byte ordering pattern and PAD patterns are 8 bits in length.

        The second configuration is with 8B/10B decoding enabled and the word aligner set to automatic synchronization state machine mode.  In this configuration, the byte ordering pattern and PAD patterns will be 9 bits in length.  These 9 bits represent the decoded code group, concatenating the control code indicator value with the 8-bit data byte.  Thus if you are using an 8B/10B control, or K, code group for alignment, then the MSB must be a ‘1’.  If you are using an 8B/10B data, or D, code group for alignment, then the MSB must be a ‘0’.

        In the diagram on this slide, you can see that the data is sent with the byte ordering character A sent in the LSByte of the data word, in this example word1.  After being sent through the channel and coming out of the byte deserializer, the byte ordering h character A has ended up in the MSByte of word1.  So, the byte ordering block inserts the PAD pattern into the stream pushing the alignment pattern into the next byte location, the LSByte of the word2.  The remaining bytes are now ordered correctly which is reflected by the status symbol being driven high.

        This table shows the three supported configurations for using the byte ordering block in double-width mode.

        The first requires a 32-bit FPGA-transceiver interface.  It requires 8B/10B decoding disabled and the word aligner mode set to manual alignment.  In this configuration, the byte ordering pattern can be 8 or 16 bits in length and the PAD patterns is 8 bits wide.

        The second configuration also uses a 32-bit interface and manual alignment, but has 8B/10B decoding enabled.  In this configuration, the byte ordering pattern will be 9 or 18 bits in lengths and the PAD patterns will be 9 bits wide.  These 18 bits represent the concatenation of the control code indicator values with two data byte.  See the note on this slide under the table for the ordering of the signals.

        The third configuration requires a 40-bit FPGA-transceiver interface, 8B/10B decoding disabled and the word aligner mode set to manual alignment.  In this configuration, the byte ordering pattern is either 10 or 20 bits in length and the PAD patterns is 10 bits wide.

       The example on this slide again illustrates the byte ordering process.  The flow is the same as in the single-width example.

        There are two operating modes for byte ordering, word-alignment-based and user-controlled.  With word-alignment-based, the signal to perform byte ordering is automatically derived from the rx_syncstatus signal from the word aligner.  So, as soon as word alignment is completed, then byte ordering begins.

        With user-controlled byte ordering, the rx_enabyteord signal can be controlled manually by your controller logic.

        Choose the mode based on how much control you require.  If you want to manually be able to force byte ordering at any time then you need user-controlled mode.  If the only times you will need to perform byte ordering is after word alignment (say for example during start-up, after a reset or after re-synchronizing the link).