原创 Transceiver Block Clocking

Altera的StratixIVGX的Transceiver模块中增加了一个叫ATX PLL模块的东东，所以IVGX的clocking更加复杂。可以简单了解一下Transceiver Block的clocking情况，不过作为用户在进行硬件设计的时候更多关注GXB的input clk的来源，内部的clocking情况大部分情况都是“自动化”的，下面分以下几方面来介绍：

Altera老的的器件的Transceiver模块对于时钟网络，比如有txpll、rxpll等，或者叫CMU、CDR。40nm高端器件开始增加一个ATX PLL，是为了使单个Transceiver通道跑着更高的速率，以下是其简单介绍，可以看到ATX PLL位于Transceiver模块之间：

        In addition to the PLLs within the transceiver blocks, Stratix IV GX/GT devices also have PLL blocks between select transceiver blocks called Auxiliary Transmit, or ATX, PLLs.  While the CMU PLLs cover the entire range of supported data rates, the ATX PLLs cover a much narrower band.  The advantage of the ATX PLLs is very low jitter, which is key for select high-speed protocol and application requirements.  There are up to 4 ATX PLLs in a Stratix IV GX device, 2 per side, supporting data rates in the range of 5 to 6.375 Gbps.  The Stratix IV GT devices have all 4 6G ATX PLLs plus an additional 2 ATX PLLs, 1 on each side, supporting data rates in the range of 9.95 to 11.3 Gbps.  Even when an ATX PLL is used, you can supported lower data rates by using built in clock dividers.

        The example on this page shows one side of a Stratix IV GT device with the ATX PLLs sitting between the transceiver blocks.  The 6G ATX PLLs are in the middle and in the bottom portion of the device while the 10G ATX PLL is in the top portion of the device.  The data rate that can be supported by a particular channel is dependent on its position with respect to the ATX PLLs.   Please see the device Stratix IV handbook for more details.  If you are in a Stratix IV GX device, then check the device handbook to see exactly which 6G ATX PLLs your device contains.

        Having these options for PLL choices allows you to match the PLL to your application, depending on your data rate or jitter requirements.

介绍完ATX PLL（CMU和CDR省略），下面来看一个Transceiver其输入参考时钟源都有哪些：

图中有四个方向给Transceiver的各TX CMU PLLs、RX CDR以及ATX PLLs提供参考时钟，需要注意的是ATX PLL的参考时钟只能由ITB来提供。第一种即refclk不用说这是专门给Transceiver提供参考时钟的，Altera推荐最好由这些引脚来提供参考时钟，但是当CMU用作Transceiver通道(这是StratixIVGX新用法)时refclks不能再用作时钟，而是作为这类Transceiver通道的数据通道。第二种就是GCLK即全局时钟，就是在全局时钟引脚上驱动进来的时钟，QuartusII软件会自动将从clk引脚进来的时钟布线到GCLK时钟网络。Each CMU channel, CDR and ATX PLL can then derive its own input reference clock from a separate global clock line。而且允许单端时钟输入。第三种就是PLL层叠时钟，一侧（左右两侧）的PLL输出可以作为同一侧Transceiver的输入参考时钟源（在老的器件比如ArriaGX似乎就不支持这样使用），这样做的好处是增加了输入参考时钟频率种类，因为CMU PLLs、CDRs以及ATX PLLs的倍频因子是非常有限的，当然其不利就是增加了发送端的jitter。最后一中就是ITB（我记得老型号器件的叫法还是有区别的），下面是其简单说明：

        On the sides of the FPGA that contains transceivers, you will find ITB clock lines.  These allow each refclk input to be carried to other transceiver blocks on the same side of the FPGA, increasing the clocking flexibility.  This is especially true in cases where you are implementing the same protocols in multiple transceiver blocks or different protocols but deriving their clocks from the same source.  Each refclk pin drives its on ITB clock line, for a maximum of 8 ITB clock lines in the largest Stratix IV GX/GT device.  Once on an ITB clock line, any CMU PLL, CDR or ATX PLL on that side of the device can access it.  Since ATX PLLs do not have their own refclk pins, they can only access refclk pins by means of ITB clock lines.

最后给一个总结：

        Summarize all of the clocks that line the FPGA fabric to transceiver interface, clocks to consider when connecting your transceiver block to your logic. 

        First, you have the input reference clocks to the 2 CMU channels and the 4 CDRs, pll_inclk and rx_cruclk.  These clocks could share the same reference clock if you desire or they can each be driven by their own separate clock sources.  Remember they can come from the dedicated refclk pins or from the FPGA fabric.

        The recovered parallel clock from the CDR can feed the FPGA fabric as rx_clkout.  The low-speed clock from the CMU feeds the core as tx_clkout for a non-bonded channel and coreclkout for bonded channels.

        Next you need to drive the write clock of the transmit phase compensation FIFO.  This clock can be tied directly to tx_clkout or coreclkout.  You can also enable tx_coreclk if you want to use your own internal clock.  To drive the receive phase compensation FIFO read clock, you can tie this input directly to rx_clkout, tx_clkout or coreclkout.  You can enable rx_coreclk when using your own internal clock.

        Finally, there’s fixedclk which is used for PCIe, cal_blk_clk which I will talk about in a few slides and reconfig_clk which is used in dynamic reconfiguration of the transceivers.