原创 【博客大赛】使用ALTERA专用时钟控制模块消除时钟问题

tx_clk_to_the_tse_mac <= enet_clk_125mhz when('1' = eth_mode_from_the_tse_mac) else -- GbE Mode = 125MHz clock

                   enet_clk_2p5mhz when('1' = ena_10_from_the_tse_mac) else   -- 10Mb Mode = 2.5MHz clock

                   enet_clk_25mhz;                                    -- 100Mb Mode = 25MHz clock

blk_enet_clkctrl: block

    signal

      enet_clkctrl_cs

        : std_logic_vector(1 downto 0) := (others => '0');

  begin

    enet_clkctrl_cs <= "10" when ('1' = eth_mode_from_the_tse_mac) else

      "11" when ('1' = ena_10_from_the_tse_mac) else

      "00";

    inst_enet_clkctrl: component enet_clkctrl

      PORT MAP

      (

        clkselect                => enet_clkctrl_cs,

        inclk0x                  => CLKIN_25MHZ,

        inclk1x                  => '0',

        inclk2x                  => enet_clk_125mhz,

        inclk3x                  => enet_clk_2p5mhz,

        outclk                   => tx_clk_to_the_tse_mac

      );

    end block;