原创 design compiler bus naming

 2013-5-14 10:10  3765 5 5 分类: 工程师职场

变量	作用	影响的命令	举例
bus_range_separator_style
bus_multiple_separator_style
bus_inference_descending_sort	一个port bus的成员如何排列	read(对erilog没有用) write(仅仅对vhdl)	如果bus_inference_style 设置为%s[%d],那么ports A[1] A[2] A[3] and A[4]将会引入一个叫做A的bus，而bus_inference_descending_sort 就会影响A[4:1]还是A[1:4]
bus_minus_style	read -vhdl
bus_multiple_separator_style	确定multibit cell的名字，和multibit有关影响multibit mapping，和bus_range_separator_style, bus_naming_style有关		如果bus_range_separator_style设置为":"， bus_naming_style设置为"%s[%d]", bus_multiple_separator_style设置为","，则cells named q[0],q[1],q[2],q[5],q[6],q[7] 将会packed into 6-bit wide cell， cell的名字就是q[0:2,5；7]
bus_naming_style	specifies the style to use in naming and idividual port member,net member,cell instance member of and edif array, or of verilog/vhdl vector,命名bus中member	read write (only edif)
bus_range_separator_style	只影响edif网表	read write (only edif)
bus_dimension_separator_style
define_name_rules	-target_bus_style
bus_inference_style	如何将单个的bit into a port bus	read(除了.db和vhdl) write(仅仅对vhdl)	其实就是一个模式匹配