原创 如何在SignalTAP II中保留特定节点 （verilog和VHDL禁止节点优化）

    使用Start Analysis & Elaboration代替Start Analysis & Synthesis可以显著缩短编译时间，对于添加节点来说，效果是相同的。原理如下： riple

Go to the Processing menu, point to Start and select Start Analysis & Elaboration to compile the design.
Before you can connect the ELA to signals in your design, you must first compile the design to build the node database. For this step, you do not need to fit the design completely. The Start Analysis & Elaboration command builds the node database, but stops before the fitting step.

    可以简单的认为：Start Analysis & Synthesis = Start Analysis & Elaboration + Mapping。Start Analysis & Elaboration可以建立未经过器件结构映射的设计数据库，而Start Analysis & Synthesis建立的是经过器件结构映射和优化的设计数据库。 riple

    同样，如果只需要观察一个设计的层次关系图，也可以使用这种方法加快速度。 riple

    同样，如果只需要观察一个设计的RTL视图，不需要观察Technology Map视图，也可以使用这种方法加快速度。 riple

背景资料：Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems riple

    以前遇到过几次类似问题，只知道关闭一下就可以通过，但是没搞清原理。在Altera的一篇文档里找到了答案： riple

In the Settings dialog box, under the Compilation Process Settings section, select Incremental Compilation. Set the Incremental Compilation option to Off.
By turning off the Incremental Compilation option, pre-synthesis signals can be added to the SignalTap II ELA in the later sections. Pre-synthesis signals exist after design elaboration, but before any synthesis optimizations are done. This set of signals should reflect your register transfer level (RTL) signals.

背景资料：Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems riple

    在使用SignalTAP II的过程中，我经常发现一些用于调试的逻辑（比如调试用的计数器）会被优化掉，不能出现在调试波形中。在Altera的一篇文档中，发现了以下关键信息： riple

In the logic synthesis stage, the Quartus II software may optimize away signals that you are trying to analyze with the SignalTap II Embedded Logic Analyzer. If this occurs, you will see a compilation error. You can force the Quartus II software to preserve these signals by adding the keep or preserve attribute in the source HDL to the signals you want to monitor.

The keep attribute is used for a wire or net node. For example:
In Verilog:
    wire my_wire /* synthesis keep = 1 */:
In VHDL:
    signal my_signal: bit;
    attribute syn_keep : boolean;
    attribute syn_keep of my_signal: signal is true;

The preserve attribute is used for a register. For example:
In Verilog:
    reg my_reg /* synthesis preserve = 1 */:
In VHDL:
    signal my_reg: stdlogic;
    attribute preserve : boolean;
    attribute preserve of my_signal: signal is true;

背景资料：Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems riple