原创基于FPGA的数字钟设计

 2006-12-9 21:15  6431 4 9 分类: FPGA/CPLD

本文所设计的数字钟具有通过reset键对时、分、秒调整功能.该设计分为六个部分：六进制计数器 counter6，十进制计数器 counter10 ，二四进制计数器 counter24，时钟模块 bclock， LED扫描显示模块 ledctrl。设计使用VHDL 语言，程序代码如下：

--*****************************************************************

--模块名 : 顶层设计

--文件名: myclock.vhd

--时间:2006年12月9日

--*********************************************************************

library ieee;
use ieee.std_logic_1164.all;
entity myclock is
port(clk1,clk2,reset:in std_logic; --clk1为计数脉冲,clk2为LED扫描脉冲;
     hh_set:in std_logic_vector(1 downto 0);             --时高位调整;
     mh_set,sh_set:in std_logic_vector(2 downto 0);     --分,秒高位调整;
     hl_set,ml_set,sl_set:in std_logic_vector(3 downto 0); --时,分,秒低位调整;
     led_dp:out std_logic;                                        --LED小数点;
     sel:out std_logic_vector(2 downto 0);        --送三-八译码生成位选信号;
     seg:out std_logic_vector(6 downto 0));       --段码;
end myclock;
architecture one of myclock is
component bclock is
      port(clk,reset:in std_logic;
        hhin:in std_logic_vector(1 downto 0);
        mhin,shin:in std_logic_vector(2 downto 0);
       hlin, mlin,slin:in std_logic_vector(3 downto 0);
        hho: out std_logic_vector(1 downto 0);
        mho,sho:out std_logic_vector(2 downto 0);
        hlo,mlo,slo:out std_logic_vector(3 downto 0));
end component bclock;
component ledctrl is
port(clk:in std_logic;
       hh:in std_logic_vector(1 downto 0);
       mh,sh:in std_logic_vector(2 downto 0);
       hl,ml,sl:in std_logic_vector(3 downto 0);
       dp:out std_logic;
       selo:out std_logic_vector(2 downto 0);
       sego:out std_logic_vector(6 downto 0));
end component ledctrl;
signal hh1:std_logic_vector(1 downto 0);
signal mh1,sh1:std_logic_vector(2 downto 0);
signal hl1,ml1,sl1:std_logic_vector(3 downto 0);
begin
u1:bclock port map(clk1,reset,hh_set,mh_set,sh_set,hl_set,ml_set,sl_set,hh1,mh1,sh1,hl1,ml1,sl1);
u2:ledctrl port map(clk2,hh1,mh1,sh1,hl1,ml1,sl1,led_dp,sel,seg);
end one;

--*********************************************************************

--模块名 : 十进制数器

--文件名: counter10.vhd

--时间:2006年12月9日

--*********************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter10 is
port(clk,reset:in std_logic;
        din:in std_logic_vector(3 downto 0);
        c:out std_logic;
        dout:out std_logic_vector(3 downto 0));
end counter10;
architecture one of counter10 is
signal dd:std_logic_vector(3 downto 0);
signal c1:std_logic;
begin
process(clk,reset) is
begin
if reset='1' then dd<=din;c1<='0';
elsif rising_edge(clk) then
    if dd="1001" then dd<="0000";c1<='1';
    else dd<=dd+1;c1<='0';
    end if;
end if;
end process;
dout<=dd;c<=c1;
end one;

--*****************************************************

--模块名 : 六进制计数器

--文件名: counter6.vhd

--时间:2006年12月9日

--******************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter6 is
port(clk,reset:in std_logic;
        din:in std_logic_vector(2 downto 0);
        c:out std_logic;
        dout:out std_logic_vector(2 downto 0));
end counter6;
architecture one of counter6 is
signal dd:std_logic_vector(2 downto 0);
signal c1:std_logic;
begin
process(clk,reset) is
begin
if reset='1' then dd<=din;c1<='0';
elsif rising_edge(clk) then
    if dd="101" then dd<="000";c1<='1';
    else dd<=dd+1;c1<='0';
    end if;
end if;
end process;
dout<=dd;c<=c1;
end one;

--*****************************************************

--模块名 : 二十四进制数器

--文件名: counter24.vhd

--时间:2006年12月9日

--******************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter24 is
   port(clk,reset:in std_logic;
        dhin:in std_logic_vector(1 downto 0);
        dlin:in std_logic_vector(3 downto 0);
        dh:out std_logic_vector(1 downto 0);
        dl:out std_logic_vector(3 downto 0));
end counter24;
architecture one of counter24 is
signal dl1:std_logic_vector(3 downto 0);
signal dh1:std_logic_vector(1 downto 0);begin
process(clk,reset) is
begin
if reset='1' then dl1<=dlin;dh1<=dhin;
elsif rising_edge(clk) then
if dh1="10"and dl1="0011" then dl1<="0000"; dh1<="00";
    elsif dl1="1001" then dl1<="0000";dh1<=dh1+1;
    else dl1<=dl1+1;
end if;
end if;
end process;
dh<=dh1;dl<=dl1;
end one;

--*******************************************************

--模块名 : 时钟模块

--文件名: bclock.vhd

--时间:2006年12月9日

--*******************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bclock is
   port(clk,reset:in std_logic;
        hhin:in std_logic_vector(1 downto 0);
        mhin,shin:in std_logic_vector(2 downto 0);
        hlin, mlin,slin:in std_logic_vector(3 downto 0);
        hho: out std_logic_vector(1 downto 0);
        mho,sho:out std_logic_vector(2 downto 0);
        hlo,mlo,slo:out std_logic_vector(3 downto 0));
end bclock;
architecture one of bclock is
component counter10 is
port(clk,reset:in std_logic;
        din:in std_logic_vector(3 downto 0);
        c:out std_logic;
        dout:out std_logic_vector(3 downto 0));
end component counter10;
component counter6 is
port(clk,reset:in std_logic;
        din:in std_logic_vector(2 downto 0);
        c:out std_logic;
        dout:out std_logic_vector(2 downto 0));
end component counter6;
component counter24 is
   port(clk,reset:in std_logic;
        dhin:in std_logic_vector(1 downto 0);
        dlin:in std_logic_vector(3 downto 0);
        dh:out std_logic_vector(1 downto 0);
        dl:out std_logic_vector(3 downto 0));
end component counter24;
signal csl,csh,cml,cmh:std_logic;
begin
   u1:counter10 port map(clk,reset,slin,csl,slo);
   u2:counter6 port map(csl,reset,shin,csh,sho);
   u3:counter10 port map(csh,reset,mlin,cml,mlo);
   u4:counter6 port map(cml,reset,mhin,cmh,mho);
   u5:counter24 port map(cmh,reset,hhin,hlin,hho,hlo);

end one;

--******************************************************

--模块名 : LED扫描显示模块

--文件名:ledctrl.vhd

--时间:2006年12月9日

--*********************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ledctrl is
port(clk:in std_logic;
       hh:in std_logic_vector(1 downto 0);
       mh,sh:in std_logic_vector(2 downto 0);
       hl,ml,sl:in std_logic_vector(3 downto 0);
       dp:out std_logic;
       selo:out std_logic_vector(2 downto 0);
       sego:out std_logic_vector(6 downto 0));
end ledctrl;
architecture one of ledctrl is
signal ledon:std_logic_vector(3 downto 0);
signal count:std_logic_vector(2 downto 0);
begin
process(clk) is
begin
if rising_edge(clk) then
   if count="101" then count<="000";
   else count<=count+1;
   end if;
end if;
end process;
selo<=count;
ledon<=sl when count="000" else
       '0'&sh when count="001" else
       ml when count="010" else
       '0'&mh when count="011" else
       hl when count="100" else
       "00"&hh when count="101" else
       "000" ;
dp<='1' when count="010" or count="100" else
    '0';
sego<="0111111" when ledon="0000" else
      "0000110" when ledon="0001" else
      "1011011" when ledon="0010" else
      "1001111" when ledon="0011" else
      "1100110" when ledon="0100" else
      "1101101" when ledon="0101" else
      "1111101" when ledon="0110" else
      "0000111" when ledon="0111" else
      "1111111" when ledon="1000" else
      "1101111" when ledon="1001" else
      "0000000";
end one;
以上便是全部代码，错误难免，敬请指正.