原创 功能仿真是正确的，时序仿真时没有输出！求救高手知道！

我刚刚编的程序，终于学会怎样进行时序仿真的，可是谁知道功能仿真是正确的，时序仿真的时候确没有输出结果，我把我的源代码传上来，肯请高手们帮我看一下我应该从那找错！

源代码：

/*It is a program of series input data to parallel out data,
which is used in 16DAPSK*/
`timescale 1us/1ns
module series_to_parallel(series_in,
    convert_clk,
    out_clk,
     convert_rst,
     parallel_out,
     convert_out,
     convert_begin,
              busy);
input series_in;
input convert_clk;
input out_clk;
input convert_rst;
input convert_begin;
output[3:0] parallel_out;
output[3:0] convert_out;
output busy;
reg[3:0] parallel_out;
reg[3:0] convert_out;
reg busy;
reg [5:0] shift_state;
//reg convert_begin;
parameter shift_state_begin="6"'b100000;
parameter shift_state_bit0=6'b000010;
parameter shift_state_bit1=6'b000100;
parameter shift_state_bit2=6'b001000;
parameter shift_state_bit3=6'b010000;
parameter shift_state_end= 6'b000001;
always @(posedge convert_rst or posedge convert_clk)
begin
 if(convert_rst)
 begin
   //busy<=1'b1;
   //convert_begin<=1'b1;
   if(convert_begin)
      begin
         shift_state<=shift_state_begin;
         parallel_out<=4'b0000;
      end
    else
      begin
          shift_state<=shift_state_end;
          parallel_out<=4'b0000;
      end
    end
    else
     begin
       case(shift_state)
       
   shift_state_begin:
   begin
    if(convert_begin)
     begin
      shift_state<=shift_state_bit3;
      busy<=1'b1;
     end
    else
     begin
      shift_state<=shift_state_end; 
      busy<=1'b0;
     end  
   end 
   shift_state_bit3:
   begin
    if(convert_begin)
     begin
      parallel_out[3]<=series_in;
      shift_state<=shift_state_bit2;
      busy<=1'b1;
     end
    else
     begin
      shift_state<=shift_state_end;
      busy<=1'b0;
     end
   end 
   shift_state_bit2:
   begin
    if(convert_begin)
     begin
      parallel_out[2]<=series_in;
      shift_state<=shift_state_bit1;
      busy<=1'b1;
     end
    else
        begin
      shift_state<=shift_state_end;
      busy<=1'b0;
     end
   end
   shift_state_bit1:
   begin
    if(convert_begin)
     begin
      parallel_out[1]<=series_in;
      shift_state<=shift_state_bit0;
      busy<=1'b1;
     end
    else
     begin
      shift_state<=shift_state_end;
      busy<=1'b0;
     end
   end
   shift_state_bit0:
   begin
    if(convert_begin)
    begin
     parallel_out[0]<=series_in;
     shift_state<=shift_state_bit3;
     busy<=1'b1;
    end
    else
     begin
      shift_state<=shift_state_end;
      busy<=1'b0;
     end
   end
   shift_state_end:
   begin
    if(convert_begin)
     begin
      shift_state<=shift_state_begin;
      busy<=1'b1;
     end
    else
     begin
     shift_state<=shift_state_end;
      busy<=1'b0;
     end
   end
   default:
    begin
     shift_state<=shift_state_end;
     //convert_begin<=1'b0;
    end
   
   endcase
 end
 //busy<=1'b0;
end
//?????????1/4??????
always@(posedge out_clk or posedge convert_rst)
   begin
       if(convert_rst)
             convert_out<=4'b0000;
        else
             convert_out<=parallel_out;
   end

endmodule
    
    

testbench代码：

`timescale 1us/1ns //时间单位为500ns，不知道那个精度时间是什么意思

module test_series_to_pallel;
//`include "series_to_parallel.v"
reg test_series_in;
reg test_convert_clk;
reg test_convert_rst;
reg out_clk;
wire[3:0] test_parallel_out;
wire[3:0] convert_out;
reg convert_begin;
wire test_busy;
parameter half_period="1";
initial
begin
test_convert_clk="0";
out_clk="0";
end

initial
begin
#1 test_convert_rst="1";
#1 test_convert_rst="0";
end
initial
begin
#1 convert_begin="1";
#400 convert_begin="0";
end
always #half_period test_convert_clk=~test_convert_clk;
always #4 out_clk=~out_clk;
always @(negedge test_convert_clk)
begin
test_series_in={$random}%2;
end
series_to_parallel test_series_to_parallel(.series_in(test_series_in),
                   .convert_clk(test_convert_clk),
                    .out_clk(out_clk),
                   .convert_rst(test_convert_rst),
                   .parallel_out(test_parallel_out),
                   .convert_out(convert_out),
                   .convert_begin(convert_begin),
                   .busy(test_busy));
endmodule

全编译的时候出现的警告：

Warning: Verilog HDL Always Construct warning at series_to_parallel.v(37): variable "convert_begin" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Timing Analysis found one or more latches implemented as combinational loops
 Warning: Node "shift_state.shift_state_end~7" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
 Info: Assuming node "convert_clk" is an undefined clock
 Info: Assuming node "out_clk" is an undefined clock