8051 IP核(VHDL)<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
1.MC8051
MC8051出新版本(1.5)了!
以下是1.5版的更新说明:
September 2006: Oregano Systems - Design & Consulting GesmbH
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Changes:
- When an interrupt is pending and the instruction executed
is RETI or a write access to IE or IP one more instruction
is executed before vectoring to the interrupt routine.
- The synchronization stage of the interrupt inputs in the
timer/counter unit has been hardended with additional
series flip-flops due to the high operating frequencies
nowadays in use.
- A prescaler in the serial interface unit has been changed
to 1/12 instead of 1/16 to conform to mode 0 databook
descriptions.
- The carry flag was incorrectly reset during a special
situation. This has been corrected.
- tmr/ctr1 erroneously used his run flag when tmr/ctr0 was
in mode 3. This has been corrected.
- In certain interrupt situations the stack pointer has
been erroneously set. This has been corrected.
http://www.oregano.at/ip/8051.htm
mc8051_design.zip https://static.assets-stash.eet-china.com/album/old-resources/2009/2/10/196f0b76-cfd6-4dc4-9719-b5dc33108a98.zip
2.C8051
The C8051 is a fully functional 8-bit embedded controller that executes all ASM51 instructions and has the same instruction set as the <?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />80C31. The C8051 serves software and hardware interrupts, provides an interface for serial communications and a timer system.
The C8051 is the microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking and with no internal tri-states. Reset is also synchronous. Therefore scan insertion is straightforward.
http://www.evatronix.pl/products/docs.html?id=0&product=QzgwNTE=
C8051(VHDL).rar https://static.assets-stash.eet-china.com/album/old-resources/2009/2/10/c039355a-24f3-42c1-85f2-25ad10ee87b3.rar
用户347042 2011-5-21 00:53
用户116143 2009-10-8 09:05