LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY maxii_lamp2 IS PORT( clk : IN STD_LOGIC; leddrv : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END maxii_lamp2;
ARCHITECTURE maxii_lamp2 OF maxii_lamp2 IS SIGNAL reg : STD_LOGIC_VECTOR(7 DOWNTO 0) :="00000001"; BEGIN
leddrv <= reg;
PROCESS(clk) VARIABLE cnt : INTEGER RANGE 0 TO 50000000 :=0; BEGIN IF clk'EVENT AND clk='1' THEN cnt := cnt+1; IF cnt="50000000" THEN cnt := 0; reg <= reg(6 DOWNTO 0)®(7); END IF; END IF; END PROCESS;
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