>
>We haven't spoken before so forgive my intruding.
>
>My name is Jilly and I am launching the activities of KTHR which has a global specialisation in search and selection for the Semiconductor industry.
>
>Please find below a brief introducton of KTHR for your further understanding of our business:
>As one of the leading IC human resource consulting companies, KTHR has been focusing on the middle to senior level talents searches in the Asia market, covering <?xml:namespace prefix = st1 ns = "urn:schemas-microsoft-com:office:smarttags" />Beijing, Shanghai, Shenzhen, and Singapore. Clients are mainly Europe and American Semiconductor players such as TI,ADI,Cisco,Conexant,and Agere, as well as some IC design houses. KTHR's large network and resource database enable a talent made searches for the clients from IC design, IC application (SoC and embedded software), IC manufactory, IC Sales & Marketing, Engineering positions etc.
>
>As we are expanding in the China market, I am keen to get to know you in order to see whether you are open to discuss the possibility of yourself working for us.
>
>Currently, we have those relevant positions for your reference:
>
>
>1.高级FPGA 设计工程师 (Senior FPGA design engineer )(急聘)－北京 （NO.12-某美资IC设计公司,全球60家最具潜力半导体初创公司之一）
>
>职位要求：
>a.具有3-5年大规模、高速专用FPGA的设计经验， 熟悉FPGA的设计开发流程，熟悉Verilog语言，熟悉Xilinx/Altera器件应用，熟悉相关综合仿真软件；
>b.熟悉多数总线协议，如：I2C、PCI、USB、存储器（如SRAM、SDRAM）控制总线等；
>c.在以下相关领域中有经验者优先：熟悉Ehernet物理层协议，并有相关设计经验；熟悉SOC架构，并有嵌入CPU设计实现经验；熟悉音视频相关标准，并有相关实现经验；熟悉图像处理、视频压缩算法，并有相关实现经验；
>d.计算机、通信、电子及相关专业本科及本科以上学历，3年以上工作经验；
>e.良好的模拟数字电路基础；良好的英文阅读和听说能力；有良好的沟通协作能力和敬业精神。
>f.能独立思考及完成项目。
>
>职位描述：设计大规模专用FPGA
>
>--------------------------------------------------------------
>
2 ASIC设计工程师/ASIC Design Engineer （上海 No 32 美资公司）
Responsibilities:
1. Micro-architecture design & specification design
2. RTL Coding and verification
3. RTL Synthesis and Static Timing Analysis
4. Matlab and C/C++ knowledge.
Requirements:
1. BSEE minimum 3+year or MSEE minimum 2+year experience
2. Familiar with ASIC Design Flow
3. ASIC digital design experience with RTL coding
4. Familiar with Linux/Unix, Perl/Tcl
5. Familiar with Algorithm to RTL implementation.
> >
>--------------------------------------------------------------
>
>3.高级硬件工程师 （上海，NO.54-某著名美资IC公司）
>
>职位要求：
>a.电子相关专业硕士以上学历，5年以上硬件开发经验；
>b.精通高速模拟RF和数字电路设计，具有丰富的系统级调试经验；
>c.熟练掌握XILINX，ALTERA以及LATTICE等公司的高端FPGA芯片的特性和各自特点，以及各家的FPGA开发工具；
>d.具有CPU和MCU方面的设计调试经验；
>e.熟练使用通用仪器和网络协议分析仪；
>f.具有丰富的网络方面的知识；
>g.具有很强的独立工作能力和动手能力和良好的团队合作精神，善于沟通，能承受工作压力。
>
>职位描述： 主要职责：
>a.根据项目要求，负责搭建芯片验证平台和芯片演示平台，包括电路原理图设计，指导PCB工程师绘制高速PCB，调试电路板；
>b.配合ASIC工程师进行芯片验证以及验证平台的维护；
>c.配合软件工程师进行软件调试；
>
>--------------------------------------------------------------
>
>4 Hardware Engineer (ASIC/FPGA Design Verification Engineer) （NO.53-某美资世界顶级IC公司）
>公司简介：
>工作地点： SHANGHAI
>职位要求： Skills required:
>- Prior significant verification experience on complex ASICs.
>- Good background in networking concepts.
>- Experience with Vera/Specman and Verilog.
>- Chip and system and test experience.
>- Programming and scripting skills.
>- Good planning skills (well partioned designs, well organized code)
>- Outstanding written and verbal communication skills
>- Capability of critical thinking, challenging design intent
>
>Education:
>MSEE with 2+ yrs relevant experience
>
>职位描述： Participate in architecture and design verification of complex networking ASIC. Responsibilities include:
>- Architecture/Micro-Architecture definition
>- Standalone and Integrated functional verification;
>- Documentation and review of Verification architecture and testplans
>- Develop verification environment (models, checkers, packet manager) using Specman/Vera
>- Develop random, pseudo-random and directed tests
>- Establish verification effectiveness using assertion/functional/code coverage and code reviews
>- RTL and gates simulation, debug and root cause
>- Regression triage and debug
>- Formal verification and equivalence checking.
>- Lab debug and design validation
>
>--------------------------------------------------------------
>5 Digital ic design engineer 上海，某世界半导体行业前20公司
Job Responsibilities
Duties will include working within a Product Development Team to perform (design, layout, and evaluate) architectural definition, digital logic design, and verification. Candidate will be involved in upfront product planning activities including architectural tradeoffs, die size estimation, packaging selection, and technology assessment. As a member of a design team, candidate will be responsible for managing the design from concept to product launch.
Functional/Industry Knowledge
Required:
- Minimum of 4-6 years Digital IC Design experience in a product development environment
- Proven Digital IC Design skills
- Must be familiar with RTL coding, synthesis, static timing analysis, simulation, audits, timing closure, CAD tools, and design support
- Must be willing to follow a structured design approach including design for reuse and provide thorough design documentation
- Strong written and verbal English communication skills
- Serdes or GbE Phy knowledge is preferred
>--------------------------------------------------------------
>
>6 .IC Design Engineer (Senior) （上海，NO.27-某美资IC设计公司）
>
>Requirements:
>a. BS Degree or above in EE or equivalent;
>b. More than 3 years working experience on digital logic IC design;
>c. At least own design experience on one of below, MCU, RFID tag, or Digital Signal Processing;
>d. Familiar with whole RTL design flow is a must
>e. Hands-on experience on RTL coding, and verification tasks
>f. Hands-on experience on EDA tools such as NC-Verilog, Design Compiler;
>g, Hands-on experience on FPGA verification;
>h. Familiar with RFID tag is a plus;
>i. Team work and quick learner is a must
>
>--------------------------------------------------------------
>
>7 视频软件工程师 （北京，NO.40-某美资留学生创业公司）
工作职责/任务描述:
作为优秀研发团队的一员，该职位主要负责芯片视频处理，图像处理和应用软件的创新性研发。团队需要不同层次水平的通信软件工程师的加入，同时该职位将可能担负多层次责任。
要求：
1. 电子类学士/电子工程硕士，电子和计算机科学专业，3年以上工作经验；
2. 精通嵌入式系统软件研发和C/C++编程；
4. 拥有ASIC/FPGA实时嵌入式软件开发经验；
5. 底层网络开发、MPEG、图像或视频应用经验优先；
6. 从事底层开发需掌握ARM，从事应用工程师职位需熟悉Linux 或 WinCE.
>--------------------------------------------------------------
>
>8 ASIC设计主管工程师 （上海,NO.47-某著名IC公司）
>
>职位要求：
>a.电子工程相关专业，硕士以上，5年以上相关工作经验；
>b.精通Verilog/VHDL编程；
>c.有CPU/MCU开发经验，熟悉8/16/32位CPU/MCU（8051或ARM）架构和开发调试系统；
>d.熟悉主流的EDA设计工具和流程，例如Cadence，Synopsys等；
>e.有FPGA设计和调试经验者优先；
>f.具备良好的交流能力和团队组织能力。
>
>职位描述：
>a.嵌入式CPU内核/MCU及平台IP的开发；
>b.嵌入式CPU内核/MCU及平台IP的验证；
>c.嵌入式CPU内核/MCU及平台IP的ASIC应用支持
>
>--------------------------------------------------------------
>
>More opportunities , please look through our website: www.kthr.com
>If you don't mind a further talk, I can call you at your convenience. Looking forward to your kind reply.
>Many thanks and Kind Regards,
>
>Jilly Ji
>
>Consultant Assistant
>
>Shanghai Key-Team Human Resources Consulting Co.,Ltd
>Add: Room F2702, SECEC,
No.86 CaoBao Road, Shanghai China>Tel: (86)021-61023600-27
>Mobile
86)159 008 77269
>Email: jilly-ji@kthr.com
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