原创 Power optimization can extend the battery life

A key measurement in a portable media player (PMP) is the time duration that it can play multimedia content from a fully charged battery (Fig. 1). With the available board area decreasing considerably and feature set increasing rapidly, designers must implement systematic power optimization strategies in both hardware and software to maximize battery life.

Saving 10 mA of current on a media player (with typical current consumption of 450 mA) while deriving power from 1800-mAh battery could increase run time by 6 min. The same figures for an audio only player (without hard disk and the full-function display replaced with a 225-mA graphic LCD) would be 22 min.

The first step in power optimization is power characterization, which helps the designer implement the strategies in an effective, methodical way (Fig. 2). For example, the hard disk uses a mechanical motor. Hence, it consumes lot of power. The latest hard disks come with many power optimization options, including different modes in which the disk can be operated, each having its own power requirement (see the table).

1. A typical audio-video system block diagram is shown.

2. This figure shows the typical power consumption figures for the key blocks of a basic media player that’s based on a generic ARM processor running Linux.

A logical power saving scheme combines the reduction of disk accesses, reading in large chunks from adjacent regions at the maximum data rate, and putting the disk into low-power mode whenever it’s idle (see the table).

For PMP applications, assume a 4-Mbit/s data rate from the disk. The player parses the video file to get the coded frame and presentation data. If we ignore the latter, the coded video and audio frames are read from the file sequentially, decoded, and displayed. The 4-Mbit/s rate defines that in 1 second, about 500 kbytes must be processed, while the read bandwidth of a hard disk is more than 10 Mbytes/s.

To implement a buffering scheme, designers must observe certain limitations. A typical disk would take an average of 2 seconds to wakeup from sleep mode. Also, the real-time video and audio output will be affected even if there’s a single buffer-miss. The data transfer must occur in a background thread with minimal processor intervention and not affecting the video playback. The user modes can change to fast-forward, rewind, and slow motion, and back to normal play. The buffering module must take all the modes into account and should switch off the disk only when it’s safe to do so.

Twin buffer scheme
A prediction-based scheme can be implemented, which requires two 16-Mbyte buffers. During start of the video playback, both the buffers are filled with video data and the hard disk is put into the sleep mode. In normal playback mode, the file will be played sequentially forward. When playback reaches half of the second buffer, a command is given to wake the disk. This step takes about 2 seconds, and the buffering module continuously polls the disk’s status. Once the disk wakes, the buffer that was previously emptied can be filled with the next 16 Mbytes of video data. When this is complete, the disk is put back into sleep mode. This process continues until the user changes the playback mode. The buffering module must detect this change and modify the prediction mechanism accordingly.

Background read
To increase the data rate from the disk, the ATA command Read Multiple can be used. Moreover, to decrease processor intervention, the DMA module can be enabled to schedule the data read in chunks of 16 sectors to the SDRAM. When a DMA transaction completes, the DMA module raises an interrupt to the processor and the interrupt service routine schedules the next DMA from the disk. This scheme uses almost no processor time and works in the background without hampering decode or playback.

The trend-prediction scheme works without buffer-miss, but only if the data-trend access is predicted and data pre-buffering is done. By analyzing the file access rate and the seek direction, the buffering module finds out which mode the user is employing, as hard-disk sleep is done only in play and slow-motion modes. During a transition from fast forward to play, the buffering module must evaluate the adequacy of data in the buffers and decide when it’s safe to put the disk into sleep mode. The inputs for making this decision are again the file access rate and seek direction. This is a critical decision and if done incorrectly, might result in a buffer miss and hence, loss of audio-video sync.

Assuming a 16-Mbyte buffer, we can calculate that it holds a data for 32(16 × 8 / 4) seconds for a 4-Mbit/s clip. In this time, the disk is active for just 4 seconds and in sleep mode for the remaining 28 seconds. So the average current used in 32 seconds is [(4 × 350) + 28 × 20] / 32, which is 61.25 mA.

For the unbuffered case, the average current is more than 180 mA, which includes the 150-mA active idle current and 350-mA read current. This means that the buffering has reduced hard-disk power by more than 65%. The saving would increase with a larger buffer and with a reduced video bit rate. In the case of audio files, a play-list of many files can be buffered and played continuously for a longer time, resulting in a greater power saving (Fig. 3).

3. Shown is the current vs. time plot with and without the buffering scheme.

LCDs consume a significant amount of power. It’s advisable to keep the display on only when needed. Also, refreshing only the part of the screen that needs to be updated instead of the entire screen offers a further reduction, such as displaying a song’s remaining play time. In addition, the user can be given the ability to control the backlight intensity of the LCD to tradeoff brightness for extra playback time.

LEDs should be used with caution in the design. They should default to "off" and only to "on" when a specific indication is given. A 330- or 470-Ω series resistance in the LED path gives maximum brightness but also drains out a current of 7 to 10 mA on a 3.3-V battery source. Here, the designer must tradeoff brightness for extra playback time.

Processor and memory block
The processor and memory block is the next major power consumer in the system. In a digital system, higher operating frequency implies higher switching loss and hence larger power consumption. For example, E = 0.5CV2F, where E refers to switching power loss, C to the effective capacitance, V to the voltage, and F to the frequency.

Clock scaling refers to setting the system’s clock frequency to the minimum possible value without compromising performance. This would require dynamic changes in the core, memory, and peripheral frequencies. The system must be intelligent enough to change the clock settings depending on the codec chosen by the user. Selecting the optimal clock frequencies could save around 5% of the total power.

The type of SDRAM chosen plays a key role in the power chart. Mobile SDRAMs are better suited for battery-based systems as they consume about 60% less power compared to conventional SDRAMs. SDRAM controllers allow designers to set the required drive strength. Hence, this should be set to the minimum while configuring the controller. SDRAM refresh period should be kept constant by reprogramming the refresh counter after each clock change.

Modern Multimedia processors typically come with multiple peripherals like UART, USB, I2C, Video Encoder, and so on. The designer must take care to switch off the peripherals that aren’t in use. Switching off the clocks to the respective modules can accomplish this, saving about 5% of the total power.

Some processors allow a range of supply voltages to be applied to their cores. For example, the data sheet would say core voltage could be between 1.2 and 1.3 V. It’s always advisable to stick to the lowest possible voltage specified. This reduces the switching losses and hence, reduce the total power consumed by the core without hampering its performance.

Static power
A good system design is one that consumes minimal static power. Unused pins should not be kept as outputs along with pull-up and -down resistors, wherever possible. Such pins must always be configured as inputs with weak pull-up/down, preventing the processor from driving and causing an unnecessary power loss in the system.

Terminations on the board must be provided only if the trace length is greater than 1/6th the electrical length. Parallel termination must be avoided if possible as it drains the power, even if the clock for which it’s provided isn’t in use. For example a 330,220-Ω parallel termination on a clock at 3.3 V would constantly drain out a 6-mA current. RC termination can be used in case of signals requiring a 50% duty cycle.

Bus hold buffers should be avoided as they have high quiescent currents and require low pull-up resistances to support their inputs. For example, if a tact switch is connected to the buffer input, a 1-mA pull up is needed on a bus hold buffer (it otherwise would have been 0.1 mA). Otherwise, it won’t allow a zero on the input. Five such switches in the system would result in a 5-mA loss, equaling 1.5% of the total power (Fig. 4). Of the available choices, a buffer with the lowest quiescent current should be chosen.

4. The power-consumption breakdown of a typical audio block is shown.

Jack sensing
Jack sensing is an important concept, one that should be considered when choosing the audio codec, many of which have built-in sensors. This gives designers additional flexibility. When neither headphone nor line out is connected, the entire audio codec can powered down, saving 10% of the total power. The codec can be powered up upon sensing the jack. If the doesn’t support sensing, it can be implemented using jack-sensing connectors.

Power-supply design
Depending on the current requirement, designers should judiciously use switching and linear regulators in the power supply block. For example, a large current requirement would call for dc-to-dc converters operating at their maximum efficiencies. Selected power selected must have low on-state losses. Care should be taken that the discharge circuitry discharges the battery to its specified capacity.

About the authors
Rajendra Turakani is a senior engineer for multimedia systems at Ittiam Systems Pvt Ltd., located in Bangalore, India. He can be reached at .
Krishna Kumar is a senior engineer for media processing, also at Ittiam Systems Pvt Ltd. in India. He can be reached at .