原创 (vsim-3601) Iteration limit reached at time 0 ns.

# ** Error: (vsim-3601) Iteration limit reached at time 540 ns.

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This error usually indicates that ModelSim is stuck in an infinite loop. In VHDL, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process. The signal changes, triggering the process, which changes the signal, which again triggers the process and the cycle continues.

The following is a simple example of a process that causes an infinite loop:

PROCESS (count)
BEGIN
count <= not count;
END PROCESS;