http://www.saleae.com/logic/

http://dangerousprototypes.com/category/logic-analyzer/

http://en.kendincos.net/video-ddnhjthn-simple-logic-analyzer-prototype-powerd-by-picoblaze.html

m4-la Logic Analyzer for Xilinx ML403

http://sourceforge.net/projects/m4-la/

m4-la is a Logic Analyzer written in VHDL for the Xilinx ML403 Development board featuring the Virtex4 FPGA. The user interface is written in C for Windows32 based platforms. Xilinx ISE and EDK tools compile the VHDL and MS Visual Studio compiles the UI.

Spartan-3E logic analyzer

I got the sump.org Logic Analyzer running on a Xilinx Spartan-3E FPGA starter kit board. This wasn't too difficult, but there were some annoying problems that I'll share with you.

Installation and setup

Once again I downloaded and installed the 32-bit ISE WebPack 11.1 software on 32-bit Linux. It's a 2.8GB download which installs to roughly 5GB. (After deleting 1GB of .xinstall folders left from the installation.. wtf..) It seems that version 12.1 was released just recently and if you're using a version other than 11.1, or another operating system, then you may of course run into fewer problems, more problems, or just different problems.

Installation ran fine as a regular user. At the end of the installation I tried to do the upgrade to version 11.5 but didn't have enough disk space left. Now I can source the settings32.sh file in the directory I installed to and then run ise, impact, and the other programs.

I struggled for a while with iMPACT not finding the built-in Xilinx programmer cable on the starter kit board. There were two issues:

USB controller firmware

Xilinx provides a driver setup script which puts files in /etc/udev/rules.d and /usr/share but I prefered to make an ebuild for the Xilinx firmware package and have added it to my Portage overlay "stuge" which was included in the official layman list on 2010-06-14. If you're not using Gentoo you could most likely run the setup_pcusb script included in the tarball without issues, but note that newer versions of udevrequire some changes in the supplied rules.

iMPACT insists on ignoring libusb

Older versions of iMPACT used a really nasty kernel driver for accessing USB devices, but now it instead prefers to use libusb for the programmer access. Yay! But not so fast...

On my system iMPACT kept trying to use the old drivers, which I did not have installed and do not want to pollute my system with. According to Xilinx this means that "libusb is not installed", which is absolutely useless of course. It's very frustrating, and typical for closed source software, that information is not sufficiently specific. They need to document the actual assumptions made by their software, instead of publishing some nonsense high level description for what is a very low level system issue. Of course libusb was installed! Stupid.

Eventually I found the problem. It seems that iMPACT uses dlopen() to load "libusb.so", which is arguably a mistake by Xilinx developers. I believe that they should specify a filename with an explicit version instead, such as "libusb-0.1.so.4". The libusb-0.12-r5 package that I had installed unfortunately did not allow the unversioned dlopen() to work. The file found by dlopen("libusb.so") was /usr/lib/libusb.so, which was a small text file (a GNU ld script) used to redirect the linker to /lib/libusb.so when I compiled programs that used libusb. Similar files exist for other libraries. dlopen() needs a binary file however, it doesn't understand the linker script, so iMPACT was unable to load libusb, quietly resorted to requiring windrvr, and complained loudly when it wasn't found. There were no error messages about the failure to load libusb. I can't fix iMPACT, so I solved the problem by doing what I should have done long ago anyway; I removed libusb-0.1 and installed the libusb-compat-0.1.3 package instead, which provides backwards compatibility for libusb-0.1 applications and uses the much improved libusb-1.0 for communication. libusb-compat installs the binary library file in /usr/lib and /usr/lib/libusb.so is a symlink to it. Once it was installed iMPACT could find the programming cable via libusb without problems.

Downloading a logic analyzer

There's not much documentation for the sump.org logic analyzer package, which is too bad since it's a really useful design. There's even a minimal and pretty open hardware made explicitly for the sump.org design, and it costs only $45; the Open Logic Sniffer. If you have use for a LA and don't already have a suitable FPGA board around then I think the OLS is amazing value for money.

On the sump.org project page there are a few different versions available for download. The experimental Spartan 3E source is for the board that I used. The zip includes source for the PC Client (Java) and for the logic analyzer hardware design (VHDL). I added a sump-analyzer-0.8.1.ebuild to my overlay that builds the client and installs a launcher script called sump-analyzer. Non-Gentooers can download the slightly older v0.8 binary package to get a pre-built analyzer.jar, or compile their own with the following commands:

$ cd client/
$ javac -encoding iso-8859-1 $(find -name '*.java')
$ jar cfm analyzer.jar Manifest.txt $(find -name '*.class' -o -name '*.png')

Another great option is the highly portable sigrok open source software, which supports the sump hardware design as well as several other logic analyzer products.

From files to hardware

The fpga directory has the VHDL code that makes up the actual logic analyzer, and the UCF (User Constraint File) that specifies how the FPGA chip is connected. Now, let's make hardware from them:

Open ISE, create a new project, select Top-level source type HDL, click Next, set Family Spartan3E, Device XC3S500E, Package FG320, Speed -4 and Preferred Language VHDL, click Next twice (skip the "Create New Source" step), and in the "Add Existing Sources" step make sure to add all files in the fpga subdirectory except for la.ucf, la.vhd and license.txt, in particular la-S3ESK.ucf and la-S3ESK.vhd must be included. When you OK the "Project Summary" then ISE should add all 23 files without problems. Double click "Configure Target Device" under "Processes: la - Behavioral" in the lower half of the Design tab in the Design panel in ISE to run through Synthesis, Place & Route, and bitstream generation.

You may get a message about no iMPACT project file, just OK that so that iMPACT starts. Double-click "Boundary Scan" in the iMPACT Flows panel, then press Ctrl-I or select File->Initialize Chain in the menu. A dialog with settings for the three discovered devices appears, just OK that too. Double click the xc3s500e icon and assign the la.bit file created by ISE. Say No to the SPI or BPI PROM question. Right-click the xc3s500e icon and select Program. OK the same properties dialog again to send the bitstream to the FPGA.

When programming has succeeded the board is a logic analyzer, and you can start capturing signals! Don't forget a level shifter or series resistors if you want to capture 5V signals.

Notes

• 
  
• SW1:0 sets baud rate: 00=115k2 01=57k6 10=38k4 11=19k2
  
• LED4:3 shows the baud rate set by SW1:0.
  
• LED1:0 shows the (active low) TX and RX signals.
  
• BTN_SOUTH is reset. LED6 shows the reset signal.
  
• LED7 shows the external clock signal. (DIP-8 socket)
  
• If capturing without an actual signal connected then remember to disable Noise Filter, or the logic analyzer doesn't see any data, and the capture seems to hang. Either apply an actual signal or close the capture, press BTN_SOUTH and then try again, making sure to disable the filter.
  
• iMPACT uses a SysV IPC semaphore to "lock" the download cable. If it isn't closed cleanly or if it crashes, it may start saying "Cable is LOCKED. Retrying..." in the log, which is of course wrong. Remove the semaphore with semget(0x240157b1,1,0),0,IPC_RMID,NULL) in a C program, or reboot, to get iMPACT to find the cable again.
  
• Look at la-S3ESK.ucf for the connections. All input channels are in the FX2 connector, but the first twelve are also on the more convenient J1, J2 and J4 headers.

http://www.freepcb.com/eebit/

This project was my entry in the Embedded Linux Journal's "Hack Embedded Linux for Fun and Prizes" contest. My goal was to create an inexpensive logic analyzer using an Altera FPGA and an embedded Linux processor from ZFLinux. Although I didn't win the contest, the logic analyzer works well and I am continuing to develop and support it just for fun. 

Latest News...

Networked Version

The contest prototype is shown below. It is a 32-channel logic analyzer based on an MZ104 processor board from Tri-M Systems, a network card, and a custom card which I designed, which I call the Analyzer PCB. The Analyzer PCB contains an FPGA, SRAM buffer, clock chip, clock switch, headers for data and clock inputs, an FPGA programming port and a PC/104 interface. The combination of the FPGA (which can be reconfigured under program control), and the MZ104 (which is essentially a complete PC running Linux), provides an exceptionally flexible instrument which can be adapted to many purposes besides logic analysis. In its current configuration it does not have a user interface, but is controlled by a remote Windows or Linux workstation over the network.

Parallel Port (PP) Version

Although the contest prototype used the ZFLinux embedded processor with an ethernet card, it is also possible to connect the Analyzer PCB directly to a host PC using the parallel port, without any other boards. This reduces the cost considerably, and is the best way to go if you just need a PC-based logic analyzer and don't want to develop a stand-alone instrument. You still have the option of using the board for lots of other purposes besides logic analysis, if you are willing to design your own logic with the Altera software. 

I modified my prototype by adding an external PP interface board. Once I verified that it worked, I designed a new PCB which incorporates the PP interface. My first prototype didn't work, apparently due to a bad FPGA, so I built a second one, which is shown below. I used a lower speed grade FPGA than the original ( -3 instead of -1 ) which is much easier to get (you can usually get it online from arrow.com.) My prototype is working nicely at 100 MHz, but I don't guarantee that you will get the same performance. The parts list still calls for the -1 part.

Blank PCBs . . . Sorry, there are no more of these available ! ! !

http://cegt201.bradley.edu/projects/proj2006/usbla/

http://www.embedds.com/picla-is-the-idea-low-cost-logic-analyzer/

PicLA is The Idea Low Cost Logic Analyzer

You’re not satisfied with the currently Logic Analyzer and would like to buy a brand new and low cost logic analyzer? OK, there is a great way here, where you can save your money and having a low cost logic analyzer here…

Yep, it’s time to develop a new PicLA logic analyzer, which it’s using an 18F2525 PIC microprocessor and a PC. In this project, the PIC is used as a hardware capture device, where it monitoring the data lines and records all the changes.

The analyzer can be operated in a “Fast Sampling” mode, which the data is being sampled into an internal 1K buffer on the PIC. There is another mode, the “Normal Sampling” or “Continuous Sampling” mode, which all the data changes are offloaded to the PC in real time.

This PicLA logic analyzer allows you to select the sampling in either 4 or 8 channels. Beside that, the 3584 or 7168 samples can be easily stored in “Fast Sampling” mode without any further modification. For the “Normal Sampling” there is no limit to the duration of the trace. The PC link will limit the “average” speed of the logic analyzer.

http://www.embedds.com/super-cool-mini-logic-analyzer/

Super Cool Mini Logic Analyzer

probably want to build a prototype to test its operation. A common logic probe is more than enough, if the circuit is not complex; otherwise, you’ll require one or more complex driving signals to exercises its operation, then you need a more powerful testing tool here!

No matter you’re home hobbyists or experimenters, you might want to build the super cool Mini Logic Analyzer. This Mini Logic Analyzer is a simple and cheap logic analyzer, where it has up to 32 channels, 128Kb of memory for each channel, sampling rate up to 100 MHz, external clock input, external trigger input and much more.

The mini logic analyzer consists of a hardware, software and firmware interface. The interface will buffer the signals that are sent from the computer’s parallel port to the circuit to be tested. Beside that, it buffers the signals that are returned from the circuit to the computer and shifts their voltage levels, where it to make it compatible with the PC’s logic levels.

The analyzer incorporates two basic functional blocks, where as:

1. 
   
2. A transistor buffer or inverter section; and
   
3. An analog switch section that feeds voltage comparators.

This mini logic analyzer also has a LED tester, where it is a simple firmware created in order to test the functionality of mini logic analyzer hardware!

http://www.embedds.com/the-remarkable-fpga-based-logic-analyzer/

The Remarkable FPGA-Based Logic Analyzer!

Most of you must have heard about logic analyzer before, but have you ever built a FPGA-based Logic Analyzer?

If you don’t know what the FPGA is, then you need to stick with us and read on the article. For your information, a field-programmable gate array (FPGA) is a semiconductor device that can be configured by the customer or designer after manufacturing, and that’s why it got the name “field-programmable.” To program an FPGA, you will need to specify how you want the chip to work with a logic circuit diagram or a source code in a hardware description language (HDL) first.

The FPGAs can be a very useful electronic component for implementing any logical function that an application-specific integrated circuit (ASIC) could perform. Furthermore, FPGAs contain programmable logic components called “logic blocks”, and a hierarchy of reconfigurable interconnects that allow the block to be wired together without any hassle at all. Logic block can be configured to perform complex combinational functions too!

Therefore, when you applied the FPGA into the logic analyzer, it would turn into a powerful tool that will benefit you in the end. What are you waiting for? Let get into the project and start the fun right now!

http://emergent.unpythonic.net/01216696167

Ever since Steve Padnos let me borrow his commercial logic analyzer at CNC Workshop, I've been wishing I had one. Several years ago, fenn alerted me to minila, which consists of GPL hardware and software, but there don't seem to (presently) be any pre-built boards available for purchase, and I don't relish soldering surface-mount parts.

Then I stumbled on this FPGA Based Logic Analyzer. It's works on the still-available, $100 "S3BOARD", and the FPGA firmware is GPL. (It also has somewhat more memory than minila, and can also go up to 200MHz. On the other hand, it doesn't have a mode like minila's "state analysis", and it transfers over slow RS232 serial instead of EPP). I got the board today, and have some initial experiences to report.

I already had Xilinx Webpack installed from earlier work on mesa boards, so it wasn't hard to build the firmware, though it did confuse me for an hour how to program the so-called "platform flash" so that the board would boot in its logic analyzer personality. (the answer involves launching a program called "impact" to create the programming file for the flash, which is different from the programming file for the FPGA itself). Later on, I modified the constraints file to add internal pull-downs on the inputs; without that, the unused inputs worked as marvelous 120Hz antennas.

Later I had trouble getting the java-based GUI to work, because it could not find the serial communication library (and also wasn't compatible with gcj for some swing-related reason; I installed sun java instead). I ultimately found the answer, though I took the coward's way--copying files into the sun java installation area--instead of the method that alistair suggested one post further down. Like rscott13, I was just so relieved to have the software working at all.

Besides the start-up problems, I've hit one small bug in the GUI: I selected only channel-group 0 and 200MHz sample rate. What I got was my desired signal interleaved with "0"s. When I selected groups 0 and 1, 200MHz sample rate worked. (so far any input signals I've tried have been at much more modest rates of under 5MHz)

The FPGA is not 5V tolerant and no protection is built into the board. The FPGA input pins do have protection diodes, though, so I designed a separate "input conditioning" board which simply consists of a 1.4K series resistor on each input signal. It also breaks the signals into the 4 groups of 8 and provides a ground for each group. This might allow something like .35mA of protection diode current per input, while the datasheet permits up to 100mA per input on up to 100 inputs (which I imagine has to be a mistake, or at least subject to other thermal limits). This simple method for 5V compatability seems to work so far.

When capturing traces of modest length (8k samples), the delay imposed by the serial link is tolerable. When getting a full 256k samples, though, you're looking more than a moment of time. My next modification may be to place a 1MB/s serial output on some unused pins--maybe the PS/2 connector--and run those through the USB-serial chip on an arduino board, which is supposed to work with rates up to 3Mb/s. (1MB/s is the fastest rate that is exactly obtainable by both devices) If that works i'll buy a dedicated TTL-serial-to-USB converter for the board.

Logic Analyzer Adapter for Xilinx boards

http://www.kdvelectronics.eu/probe_adapter/probe_adapter.html

Logic Analyzer Adapter for Xilinx boards

Description

The Intronix Logicport is a small USB-based logic analyzer. It has 34 channels, two of which can be used as clock inputs, and does state analysis at 200 MHz. Sample depth without compression is 2048 samples per channel. While the Logicport is modest in specifications, for many tasks it may well be all you need. I mainly use the Logicport for Xilinx FPGA projects.

The Logicport connects to the system under test using one of three ways:

• 
  
• The Logicport comes standard with a 38-wire flying lead probe. These are 38 individual color-coded wires - 34 signal and 4 ground wires - which you connect one by one.
  
  
• A 38-pin Mictor ("Matched Impedance Connector") adapter is also available.
  
  
• The Logicport uses a standard 40-pin IDC connector, so you may be able to use a 40-wire IDE hard drive cable as test lead if clock frequencies are low enough and your cable short enough. If you use an IDE hard drive cable as test lead, make sure the IDE cable is a full 40-wire cable, and not one with pin 20 disabled.

Logicport logic analyzer with flying leads. To the right, the Mictor adapter.

 

Problem

Plugging 38 color-coded leads on 38 header pins on my Xilinx Development Board is time-consuming and error-prone.

Solution

Instead of connecting through a flying lead probe, connect through a custom adapter.

Benefits:

• 
  
• The adapter simply plugs into the target system. No flying leads.
  
  
• The Logicport plugs into the adapter. No cables. 
  

Xilinx to Logicport adapter

Adapter, front view.	Adapter, back view.

Adapter sitting on a Xilinx ML403, using the Xilinx Generic Interface (XGI) connector. Other Xilinx developments boards feature the same connector. Please note the XGI connector is non-polarized. Make sure you do not plug in the adapter upside-down. Plugging in the adapter upside-down will short some FPGA outputs to ground, possibly damaging them.

ML403 board, with logic analyzer sitting on adapter.

This setup allows you to look at 32 signals, a clock enable and a clock inside the FPGA in real time at reasonable cost.

Ground loops

When connecting the Logicport to a circuit, you are connecting the circuit ground to the PC ground through the USB cable. If circuit ground and PC ground have a different potential, connecting them produces a ground loop. This is a general problem, which may also occur in USB oscilloscopes, for instance.

A simple solution against ground loops, sufficient for occasional use, is using a notebook with the AC cord unplugged, running off the battery. My personal  choice has been to put a 100VA isolation transformer Block TIM-100 between notebook and mains and forgetting all about ground loops. Connecting the notebook to the network using unshielded twisted pair ethernet does not break the isolation.

Availability

I neither manufacture nor sell these adapters. If you want one, you will have to make one yourself. If you wish to have the printed circuit board made for you, download the archive for the adapter and extract all files. Send the .brd file to a PCB house such as pcb-pool. The .brd file is anEagle format file. Ask for a double-sided PCB with solder mask, no silkscreen, no electrical testing.

Downloads

The schematics and board layout can be downloaded:

• 
  
• Logicport adapter for Xilinx boards. Schematics and board layout. Board dimensions are 100 mm x 38 mm.
  
  
• Sample Xilinx ISE project for ML403 board. Implements a 100 MHz ring counter.
  
• Sample Xilinx ISE project for ML505 board. Implements a 100 MHz ring counter.

You can use the sample ISE project as a simple electrical test. You should get the following waveform:

 
Ring counter output.

Last update page: October 9, 2007

34 CHANNEL LA1034 LOGICPORT LOGIC ANALYZER

http://www.pctestinstruments.com/index.htm

http://opencores.org/project,openverifla

openVeriFLA - FPGA logic analyzer :: Overview

Details

Name: openverifla
Created: Jul 31, 2007
Updated: Mar 3, 2008
SVN Updated: No data
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Library
Language: Verilog
Development status: Stable
Additional info: FPGA proven 
WishBone Compliant: No
License: GPL

http://lekernel.net/blog/?p=72

USB Logic Analyzer

http://www.sump.org/projects/analyzer/

FPGA Based Logic Analyzer

The outcome of this project is a logic analysator for home use.

The project includes the actual analyzer in VHDL (for Spartan 3 FPGA) and a PC Software for the end user. The design employs a FPGA board that can be obtained easily.

Features

• 
  
• 16 channels at 200MHz sampling rate
  
• 32 channels up to 100MHz sampling rate
  
• state analysis up to 50MHz using external clock
  
• 256KSamples memory
  
• noise filter
  
• complex serial and parallel trigger with four stages
  
• externally available sampling clock to drive add-ons (like ADCs)
  
• connects via EIA232/RS232 (works with usb to serial adapters)
  
• Java based viewing software (see PC Client for details)
  
  • 
    
  • I2C & SPI protocol analysis

Hardware

The device uses a Xilinx Spartan 3 Starter Kit (DO-SPAR3-DK) evaluation board manufactured by Digilent. It features a XC3S200-4 FPGA with 4ns propagation delay and 3840 cells. Onboard are 1MByte of 10ns SRAM and plenty connectors that can be used as signal inputs.

To construct a comparable board from scratch would be a tough task for a home project. Especially the really low price of about USD100 makes it pointless to try to compete with this "mass product". All that remains to be done is to program the FPGA. For an overview of the VHDL code see:

FPGA VHDL Model

To learn how to communicate with the analyzer read:

Communications Protocol

Client

A java client is used to access the device from almost any PC with a serial port. The client uses the RXTX library for serial port communications which is available for 34 platforms including Linux, Windows and Solaris.

It has been developed with jdk 1.4.2 but might work with older versions. More information about the client can be found on its page:

Logic Analyzer Client

License

Files found in the downloadable archives below are released under the GNU GPL.

Downloads

Packages contain all that is needed for PC client, FPGA and tester.
See history for a list of changes between versions

"Official" Version

Logic Analyzer Package v0.8 - Binary (2007-03-03)
Logic Analyzer Package v0.8 - Source (2007-03-03)

User Contributed Versions

These downloads are provided without any testing.

Altera DE2: Experimental Port to Verilog for Altera DE2 Board - Source (2007-05-21)
(Contributed by Kenneth Tsang. Uses external SRAM.)

Altera DE2: Experimental Port to Verilog for Altera DE2 Board - Source (2007-05-21)
(Contributed by Kenneth Tsang. Uses internal M4K SRAM.)

Spartan 3E: Experimental Version for New Spartan 3E Starter Kit - Source (2007-03-08)
(Contributed by Jonas Diemer. Uses internal BRAM with optional RLE.)

Archive

Logic Analyzer Package v0.7 - Source (2006-12-31)
Logic Analyzer Package v0.6 - Source (2006-08-19)
Logic Analyzer Package v0.5 - Source (2006-06-18)
Logic Analyzer Package v0.4 - Source (2006-05-23)
Logic Analyzer Package v0.3 - Source (2006-05-05)

http://gadgetforge.gadgetfactory.net/gf/project/lax/

The "Sump" Logic Analyzer supports 32 channels with 4K sample memory up to 100MHz. The included Java client application allows waveform exploration as well as SPI and I2C protocol analysis. The project is optimized to run on the Butterfly Platform hardware.

Features

• 
  
• 4K sample memory (expandable in future designs)
  
• 32 channels sampling at 100MHz
  
• 16 channels sampling at 200MHz (experimental)
  
• Four stage serial and parallel triggering
  
• External clock input
  
• Noise filter
  
• RLE built into the hardware to make the most of available memory.
  
• SPI protocol analysis (SPI debugger)
  
• I2C protocol analysis (I2C debugger)
  
• UART protocol analysis (UART debugger)
  
• State Analysis

Additional Benefits 

• 
  
• Completely Open Source hardware and software with development communities working on new functionality.
  
• Since the Logic Analyzer is built on very flexible FPGA technology it is not limited to being a Logic Analyzer. Future projects that will be supported by the same "Butterfly Light" hardware include:
  
  • 
    
  • Flash Programmer
    
  • Oscilloscope
    
  • Variable Power Supply

• 
  
• The same Butterfly Hardware can be used as a FPGA development platform supported by an Open Source community actively developing projects such as:
  
  • 
    
  • 8 bit microcontrollers
    
  • Hardware Modules to implement additional functionality such as more memory and input buffers.
    
  • 32 bit RISC processors that can run ucLinux
    
  • Java Virtual Machines to support Java development.

Limitations 

• 
  
• The FPGA can only sample 1.2V, 2.5V, and 3.3V. Any higher voltages can damage the input pins of the FPGA. Given time a plugin board will be developed to address this issue.
  
• Operation above 100MHz is not well tested.

http://www.usbee.com/suite.html

Easy to use Logic Analyzer / Oscilloscope The USBee Suite is powerful electronic signal analysis software for your USBee Test Pod.  It starts out as an easy to use Logic Analyzer and Oscilloscope and adds serial bus decoding and world class configurability that lets you solve your electronic problems quickly! Some of the serial busses that are decoded include: I2C, SPI, Async, USB, CAN, 1-Wire, PS/2, SMBus, I2S, Sync Serial and even your own Custom Busses. World-Class User Interface You look at a Logic Analyzer / Oscilloscope for extended lengths of time.  Why don't you make sure you can enjoy it at the same time?  The USBee Suite software lets you choose the look and feel of the interface and saves that information for when you come back to it again. Best of all the USBee Suite Standard is Free!

The USBee Suite Standard is a free download and will run in Demo mode without a USBee, or on any USBee SX, USBee ZX, USBee AX-Standard, USBee AX-Plus, USBee AX-Pro, USBee DX or BusBee Test Pod.  So take it for a spin.  If it has been a while since you've used your USBee, pull it out of your pocket and experience the power of the USBee Suite.   Upgrade to the USBee Suite Pro for State-of-the-Art Debugging Features! The USBee Suite Pro builds upon the rich features set of the Standard version and adds high powered capabilities such as Complex Event Searching, PacketPresenter custom packet decoder, Smart Markers, enhanced PacketPresenter API for developers, annotation capabilites, enhanced acquisition control for repeated measurements, display control, analog channel scaling, analog bus decoding, and enhanced file importing and exporting.