原创 dc_shell脚本

remove_design -all

link_library="* smic18_tt.db"
target_library=smic18_tt.db
search_path=e:/code/verilog

read_file -format verilog ./shifter/source_code/shifter.v
read_file -format verilog ./shifter/source_code/reg_wrapper.v
current_design=reg_wrapper
link

/* Create clock object */
create_clock -period 4 find(port, clk)
set_dont_touch_network find(clock, clk)
set_clock_uncertainty 0.35 find(clock, clk)

set_input_delay -clock clk -max 0.3            shift_func
set_input_delay -clock clk -min 0.3 -add_delay shift_func
set_input_delay -clock clk -max 0.3            operand_a
set_input_delay -clock clk -min 0.3 -add_delay operand_a
set_input_delay -clock clk -max 0.3            operand_b
set_input_delay -clock clk -min 0.3 -add_delay operand_b
set_output_delay -clock clk -max 0.3            operand_c
set_output_delay -clock clk -min 0.3 -add_delay operand_c

check_design
check_timing

set_fix_multiple_port_nets -all -buffer_constants

compile

check_design
report_timing > timing.txt
write -format verilog -hier -out shifter_dc.v

#############################################

#电子竞赛的伤心地，竟然在跨时钟域综合上弄了半个小时

set_false_path -from [get_clock clka] -to [get_clock clkb]

set_false_path -from [get_clock clkb] -to [get_clock clka]