原创 【转】VHDL秒表计时器

计时器的设计功能：

（1）  精度应大于1/100s

（2）  计时器的最长计时时间为1小时

       在一般的短时间计时应用中，1小时应该足够了。为此需要一个6位显示器，显示最长时间为59分59.99秒。

（3）  设置复位和启/停开关

       复位开关用来使计时器清0，并作好清0准备。启/停开关的使用方法与传统的机械计时器相同，即按一下启/停开关，启动计时器开始计时，再按一下启/停开关计时终止。复位开关可以在任何情况下使用，即使在计时过程中，只要按一下复位开关，计时进程应立即终止，并对计时器清零。

设计方案：

    为了便于描述，将整个计时控制芯片分成5个子模块：键输入子模块（keyin）,时钟产生子模块（clkgen）,控制子模块（ctrl）,定时计数子模块（cntclk）和显示子模块（disp）,各模块之间信号连接关系的方框图如下：

芯片设计：

各模块程序及生成的符号文件如下：

keyin模块设计

该模块的描述是为了产生单个复位脉冲res和启停脉冲stst.整个功能模块用两个进程语句描述。

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity keyin is

port(reset,start_stop,clk :in std_logic;

res,stst :out std_logic);

end entity;

architecture a of keyin is

signal res0,res1,stst0,stst1 :std_logic;

begin

process(clk)

begin

if(clk'event and clk='0')then

 res1<=res0;

 res0<=reset;

 stst1<=stst0;

 stst0<=start_stop;

end if;

end process;

process(res0,res1,stst0,stst1)

begin

res<=clk and res0 and (not res1);

stst<=clk and stst0 and (not stst1);

end process;

end a;

clkgen模块设计

该模块的功能是产生100Hz的计时允许信号cntclk和25Hz的宽度为1ms的键输入时钟信号keycek.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt10 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry:OUT STD_LOGIC;

          q    :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT10;

ARCHITECTURE rtl OF cnt10 IS

     SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="0000";

          ELSIF(en='1') THEN

              IF(qs="1001") THEN

                qs<= "0000";

                ca<='0';

              ELSIF(qs="1000") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt4 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry       :OUT STD_LOGIC;

          q           :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));

END CNT4;

ARCHITECTURE rtl OF cnt4 IS

     SIGNAL qs :STD_LOGIC_VECTOR(1 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="00";

          ELSIF (EN='1')THEN

              IF(qs="11") THEN

                qs<= "00";

                ca<='0';

              ELSIF(qs="10") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

                qs<=qs+1;

                ca<='0';

              END IF;

          END IF;

       END IF;

      END PROCESS;

     PROCESS(ca)

     BEGIN

        q<=qs;

        carry<=ca AND en;

     END PROCESS;

  END rtl;

ctrl子模块

该模块的功能是产生计时计数模块的计数允许信号cnten

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity ctrl is

port(sysres,res,stst,cntclk:in std_ulogic;

centen:out std_ulogic);

end ctrl;

architecture rtl of ctrl is

signal enb1:std_ulogic;

begin

process(stst,sysres,res)

begin

if(sysres='1' or res='1') then

enb1<='0';

elsif(stst'event and stst='1') then

enb1<=not enb1;

end if;

end process;

centen<=enb1 and cntclk;

end rtl;

cntblk模块设计

该模块的功能是实现计时计数，它由四个十进制计数器和两个六进制计数器串结而成。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt10 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry:OUT STD_LOGIC;

          q    :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT10;

ARCHITECTURE rtl OF cnt10 IS

     SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="0000";

          ELSIF(en='1') THEN

              IF(qs="1001") THEN

                qs<= "0000";

                ca<='0';

              ELSIF(qs="1000") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

                qs<=qs+1;

                ca<='0';

              END IF;

          END IF;

       END IF;

      END PROCESS;

     PROCESS(ca,en)

     BEGIN

        q<=qs;

        carry<=ca AND en;

     END PROCESS;

  END rtl;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY cnt6 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry       :OUT STD_LOGIC;

          q           :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT6;

ARCHITECTURE rtl OF cnt6 IS

     SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="0000";

          ELSIF(en='1')THEN

              IF(qs="0101") THEN

                qs<= "0000";

                ca<='0';

              ELSIF(qs="0100") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

                qs<=qs+1;

                ca<='0';

              END IF;

          END IF;

       END IF;

      END PROCESS;

     PROCESS(ca,en)

     BEGIN

        q<=qs;

        carry<=ca AND en;

     END PROCESS;

  END rtl;