原创 基于FPGA/CPLD的MSK调制解调的工程应用(下)

接上页:基于FPGA/CPLD的MSK调制解调的工程应用(中) module pcosqsin(clk,rst,en,iqen,p,q,sin,cos,qsin,pcos,rdy);

input clk;

input rst;

input en;

input iqen;

input[15:0] p,q;

input[15:0] sin,cos;

output[15:0] qsin,pcos;

output rdy;

reg[15:0] qsin,pcos;

reg rdy;

reg[15:0] preg,qreg;

always @ (posedge clk) begin

if(rst) begin

qsin <= 16'd0;

pcos <= 16'd0;

rdy <= 0;

end

else if(en) begin

rdy <= 1;

case(preg)

16'h7fff: pcos <= cos;

16'h8000: pcos <= ~cos + 1;

default: ;

endcase

case(qreg)

16'h7fff: qsin <= sin;

16'h8000: qsin <= ~sin + 1;

default: ;

endcase

end

else begin

qsin <= 16'd0;

pcos <= 16'd0;

rdy <= 0;

end

end

always @ (posedge clk) begin //pq两路信号缓冲一个时钟周期

if(rst) begin

preg <= 16'd0;

qreg <= 16'd0;

end

else if(iqen) begin

preg <= p;

qreg <= q;

end

else begin

preg <= 16'd0;

qreg <= 16'd0;

end

end

endmodule

module highfre(clk,rst,en,phase,rdy);

input clk;

input rst;

input en;

output[15:0] phase;

output rdy;

reg[15:0] phase;

reg rdy;

reg rdyreg;

always @ (posedge clk or posedge rst) begin

if(rst) begin

phase <= 16'h0000;

rdy <= 0;

end

else if(rdyreg) begin

rdy <= 1;

if( (phase < 16'h8000) && (phase > 16'h6087) ) begin

phase <= 16'h9b82; //-pi

end

else begin

phase <= phase + 16'h3243; //1657

end

end

else begin

phase <= 16'h0000;

rdy <= 0;

end

end

always @ (posedge clk or posedge rst) begin

if(rst) begin

rdyreg <= 0;

end

else if(en) begin

rdyreg <= 1;

end

else begin

rdyreg <= 0;

end

end

endmodule

module add(clk,rst,en,a,b,sum,rdy);

input clk;

input rst;

input en;

input[31:0] a,b;

output[32:0] sum;

output rdy;

reg[32:0] sum;

reg rdy;

always @ (posedge clk) begin

if(rst) begin

sum <= 33'd0;

rdy <= 0;

end

else if(en) begin

rdy <= 1;

sum <= {a[31],a} + {b[31],b};

end

else begin

sum <= 33'd0;

rdy <= 0;

end

end

endmodule

其中用到两个正余弦和两个乘法的IP Core.正所谓用面积换速度吧。