原创 基于FPGA/CPLD的MSK调制解调的工程应用(中)

接上页:基于FPGA/CPLD的MSK调制解调的工程应用(上) module pqvalue(clk,rst,nd,signal_in,preg,qreg,rdy);

input clk;

input rst;

input nd; //该模块工作启动信号

input[15:0] signal_in; //输入的十六位信号

output[15:0] preg;

output[15:0] qreg;

output rdy;

reg num;

reg[15:0] signal_reg;

reg[15:0] p,q;

reg[15:0] preg,qreg;

reg rdy; //输出标志位

reg rdy0;

always @ (posedge clk or posedge rst) begin

if(rst) begin

p <= 16'h7fff; //p的初始值为+1

q <= 16'h7fff; //q的初始值为+1

num <= 1;

signal_reg <= 0;

rdy0 <= 0;

end

else if(nd) begin

rdy0 <= 1;

num <= ~num;

signal_reg <= signal_in;

case( {signal_reg,signal_in} )

32'h7fff8000: if(num) q <= ~q;

else p <= ~p; //-1,+1

32'h80007fff: if(num) q <= ~q;

else p <= ~p; //+1,-1

default: ; //其它情况p和q值保持不变

endcase

end

else begin

p <= 16'h7fff; //p的初始值为+1

q <= 16'h7fff; //q的初始值为+1

num <= 1;

signal_reg <= 0;

rdy0 <= 0;

end

end

always @ (posedge clk) begin //将数据缓冲一个时钟周期后输出

if(rst) begin

preg <= 16'd0;

qreg <= 16'd0;

rdy <= 0;

end

else if(rdy0) begin

preg <= p;

qreg <= q;

rdy <= 1;

end

else begin

preg <= 16'd0;

qreg <= 16'd0;

rdy <= 0;

end

end

endmodule

module pqvalue(clk,rst,nd,signal_in,preg,qreg,rdy);

input clk;

input rst;

input nd; //该模块工作启动信号

input[15:0] signal_in; //输入的十六位信号

output[15:0] preg;

output[15:0] qreg;

output rdy;

reg num;

reg[15:0] signal_reg;

reg[15:0] p,q;

reg[15:0] preg,qreg;

reg rdy; //输出标志位

reg rdy0;

always @ (posedge clk or posedge rst) begin

if(rst) begin

p <= 16'h7fff; //p的初始值为+1

q <= 16'h7fff; //q的初始值为+1

num <= 1;

signal_reg <= 0;

rdy0 <= 0;

end

else if(nd) begin

rdy0 <= 1;

num <= ~num;

signal_reg <= signal_in;

case( {signal_reg,signal_in} )

32'h7fff8000: if(num) q <= ~q;

else p <= ~p; //-1,+1

32'h80007fff: if(num) q <= ~q;

else p <= ~p; //+1,-1

default: ; //其它情况p和q值保持不变

endcase

end

else begin

p <= 16'h7fff; //p的初始值为+1

q <= 16'h7fff; //q的初始值为+1

num <= 1;

signal_reg <= 0;

rdy0 <= 0;

end

end

always @ (posedge clk) begin //将数据缓冲一个时钟周期后输出

if(rst) begin

preg <= 16'd0;

qreg <= 16'd0;

rdy <= 0;

end

else if(rdy0) begin

preg <= p;

qreg <= q;

rdy <= 1;

end

else begin

preg <= 16'd0;

qreg <= 16'd0;

rdy <= 0;

end

end

endmodule

module phase_generate(clk,rst,en,phase,rdy);

input clk;

input rst;

input en;

output[15:0] phase;

output rdy;

reg[15:0] phase;

reg rdy;

always @ (posedge clk or posedge rst) begin

if(rst) begin

phase <= 16'h0000;

rdy <= 0;

end

else if(en) begin

rdy <= 1;

if( (phase < 16'h8000) && (phase > 16'h6087) ) begin

phase <= 16'h9b82; //-pi

end

else begin

phase <= phase + 16'h0527; //0527

end

end

else begin

phase <= 16'h0000;

rdy <= 0;

end

end

endmodule

未完，强制分页：基于FPGA/CPLD的MSK调制解调的工程应用(下)