原创 [转]BSIM device modeling

     从电荷、电势的分布出发，解二维泊松方程所得一种建立在物理原型基础上的MOS器件模型，
它考虑到了多种效应对器件行为的影响，是以物理方式来对器件的输出阻抗进行模拟的器件模型。
它不仅可以在较大的范围内模拟现有工艺的各种尺寸的器件，还可以根据设计的器件尺寸和预定的
工艺条件较好地预测器件的特性。

"BSIM3V1 －   窄沟器件、亚域值区的衬偏效应考虑较少。
"BSIM3V2 － 没有考虑漏源接触电阻、沟宽扩展量等参数随栅压、衬偏等的变化。
"Bsim3V3 － 考虑了栅压、衬偏对漏源接触电阻、沟宽扩展量等参数的影响，增加了相关的参数，提高了模型的覆盖性；采用单一方程来模拟器件从弱反型区向强反型区以及从线性区向饱和区的过渡，提高了过渡区的光滑、连续性。
     
BSIM3v3是适用于SPICE电路模拟的工业界主流的MOS器件模型，考虑以下效应：

1) 短沟、窄沟效应对域值电压的影响
2) 沟道中纵向和横向非均匀掺杂对域值电压及衬偏的影响
3) 纵向电场对迁移率的影响
4) 体电荷效应
5) 载流子速度饱和效应
6) 漏感生势垒降低效应（DIBL）
7) 沟道长度调制效应（CLM）
8) 衬底电流感生体效应（SCBE）
9) 亚域值电导
10) 漏源寄生电阻

BSIM4支持完整的DC to RFCMOS建模， 在.13工艺以下将占主流，相比BSIM3v3有以下改进：
(1) an accurate new model of the intrinsic input resistance for both RF, high-frequency analog and high-speed digital applications;

(2) flexible substrate resistance network for RF modeling;

(3) a new accurate channel thermal noise model and a noise partition model for the induced gate noise;

(4) a non-quasi-static (NQS) model that is consistent with the Rg-based RF model and a consistent AC model that accounts for the NQS effect in both transconductances and capacitances. (5) an accurate gate direct tunneling model for multiple layer gate dielectrics;

(6) a comprehensive and versatile geometrydependent parasitics model for various source/drain connections and multi-finger devices;

(7) improved model for steep vertical retrograde doping profiles;

(8) better model for pocket-implanted devices in Vth, bulk charge effect model, and Rout;

(9) asymmetrical and bias-dependent source/drain resistance, either internal or external to the intrinsic MOSFET at the user's discretion;

(10) acceptance of either the electrical or physical gate oxide thickness as the model input at the user's choice in a physically accurate maner;

(11) the quantum mechanical charge-layerthickness model for both IV and CV; (12) a more accurate mobility model for predictive modeling;

(13) a gate-induced drain/source leakage (GIDL/GISL) current model, available in BSIM for the first time;

(14) an improved unified flicker (1/f) noise model, which is smooth over all bias regions and considers the bulk charge effect;

(15) different diode IV and CV charatistics for source and drain junctions;

(16) junction diode breakdown with or without current limiting;

(17) dielectric constant of the gate dielectric as a model parameter; (18) A new scalable stress effect model for process induced stress effect; device performance becoming thus a function of the active area geometry and the location of the device in the active area;

(19) A unified current-saturation model that includes all mechanisms of current saturation- velocity saturation, velocity overshoot and source end velocity limit;

(20) A new temperature model format that allows convenient prediction of temperature effects on saturation velocity, mobility, and S/D resistances.

BSIM4团队的华人高手：
Chenming Hu
TSMC Distinguished Professor of Microelectronics University of California, Berkeley
Professional Experiences
1976-Present, Professor of Electrical Engineering, University of California, Berkeley
2001-2004, Chief Technology Officer, TSMC (Taiwan Semiconductor Manufacturing Co)
1973-1976, Assistant Professor, Massachusetts Institute of Technology
Honors and Awards
Member, US National Academy of Engineering, 1997-.
Member, Academia Sinica, Taiwan, 2004-.
IEEE Jack Morton Award (for contributions to IC reliability physics), 1997.
IEEE Solid State Circuits Award (for developing world standard transistor model), 2002.
Berkeley Distinguished Teaching Award (Berkeley抯 highest honor for teaching), 1999.
Chancellor抯 Professor Chair, University of California, Berkeley, 1998-2001.
TSMC Distinguished Professor Chair, Univ. of California, Berkeley, 2001-present.
Life Honorary Professor, Chinese Academy of Science, China, 1990-.
Honorary Professor, National Chiao Tung University, Taiwan, 2001-.
Fellow, Institute of Electrical and Electronics Engineers, 1989-.
Fellow, Institute of Physics, 1998-.
Sigma Xi Moni Ferst Award (for encouragement of research through education), 1998.
W.Y. Pan Foundation Award (for Distinguished Research), 1999.
DARPA Most Outstanding Technical Accomplishment Award (for FinFET), 2000.
R&D100 Award (for BSIM3 as one of the most significant new technologies), 1998.
IEEE Paul Rappapart Award (best paper in all Electron Devices Society journals), 2003.
Semiconductor Research Corporation Outstanding Research Award, 1994.
ISSCC Beatrice Winner Award, 2000.
Research Highlights
Led the development of transistor model, BSIM, which is the international industry standard for circuit simulation and is used in the design of most ICs worldwide with cumulative value of several hundred billion dollars. Contributed widely used IC reliability models (oxide, hot carrier, AC electromigration) and the first IC reliability simulator. Co-developed the FinFET transistor structure, which has set the record of transistor miniaturization and is expected to enable the scaling of transistors through 10nm-gate length. Supervised over 60 Ph.D. theses.
Publications
3 books, 800 research articles, conference keynote or invited talks.
Education
B.S., EE, National Taiwan University, 1968
M.S. and Ph.D., EECS, University of California, Berkeley, 1970 and 1973

For More Information:

http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html