原创 I2C-Master Core

     详细设计说明

I2C-Master Core Specification

Author: Richard Herveille
rherveille@opencores.org
Rev. 0.9
July 3, 2003

I2C-Master Core  Verilog  VHDL 源代码

I2C-Master Core  Verilog  TestBench

Introduction
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices. It is most suitable for applications requiring occasional
communication over a short distance between many devices. The I2C standard is a true
multi-master bus including collision detection and arbitration that prevents data
corruption if two or more masters attempt to control the bus simultaneously.
The interface defines 3 transmission speeds:
- Normal: 100Kbps
- Fast: 400Kbps
- High speed: 3.5Mbps
Only 100Kbps and 400Kbps modes are supported directly. For High speed special IOs
are needed. If these IOs are available and used, then High speed is also supported.
FEATURES
? Compatible with Philips I2C standard
? Multi Master Operation
? Software programmable clock frequency
? Clock Stretching and Wait state generation
? Software programmable acknowledge bit
? Interrupt or bit-polling driven byte-by-byte data-transfers
? Arbitration lost interrupt, with automatic transfer cancelation
? Start/Stop/Repeated Start/Acknowledge generation
? Start/Stop/Repeated Start detection
? Bus busy detection
? Supports 7 and 10bit addressing mode
? Operates from a wide range of input clock frequencies
? Static synchronous design
? Fully synthesizable