深入剖析barebox(U-BOOT-II)在i.MX27上的移植
writel(IMX_PLL_PD(1) |
IMX_PLL_MFD(12) |
IMX_PLL_MFI(9) |
IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL |
CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN |
CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) |
CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL |
CSCR_MSHC_SEL, CSCR)
sdram_init
#ifdef CONFIG_NAND_IMX_BOOT
ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM [ram start+15M offset] */
ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
/* skip NAND boot if not running from NFC space */
cmp pc, r0
bls ret #if(pc < r0) goto ret
cmp pc, r2
bhi ret ##if(pc > r2) goto ret
/* Move ourselves out of NFC SRAM */
ldr r1, =TEXT_BASE #0xa7f0_0000
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
1:
bl nand_boot /* Load barebox from NAND Flash */
ldr r1, =IMX_NFC_BASE - TEXT_BASE
sub r10, r10, r1 /* adjust return address from NFC SRAM */
/* to SDRAM */
#endif /* CONFIG_NAND_IMX_BOOT */
ret:
mov pc,r10
Reset函数流程如下
board_init_lowlevel函数在 arch/arm/boards/你的电路板目录下面/lowlevel.c文件中,流程如下
.text :
{
_stext = .;
_text = .;
*(.text_entry*)
*(.text_bare_init*)
*(.text*)
}
看看几个函数的申明
void __naked __section(.text_entry) exception_vectors(void)
说明exception_vectors在*(.text_entry*)节中
void __naked __bare_init reset(void)
void __bare_init nand_boot(void)
.section ".text_bare_init","ax”
.globl board_init_lowlevel
board_init_lowlevel:
#define __bare_init __section(.text_bare_init.text)
说明这三个函数在*(.text_bare_init*)节中,这样就保证了这4个关键函数在最前面的2K,不会将他们链接到其他地方去。
__barebox_initcalls_start = .;
.barebox_initcalls : { INITCALLS }
__barebox_initcalls_end = .;
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