原创 [译完] Rapid System Prototyping with FPGAs - 4.2

 2010-6-23 15:54  3296 3 6 分类: FPGA/CPLD

4.2 Common Design Challenges and Mistakes
An FPGA design mistake may be defined as a design that does not achieve the desired ratio of FPGA resource utilization (I/O, logic, memory, hard IP, resource area) and performance (speed/power) implemented within the FPGA device. The number and impact of FPGA design mistakes and oversights may be minimized by developing and consistently following a optimized FPGA design process. The design process should call out design procedures, milestones and design objectives. It should help manage and stabilize the FPGA design cycle. These design challenges most relevant to rapid development that impact the management and development of an FPGA design are listed below.

Common Design Challenges

Layout
Signal integrity
Clocks
Pin assignments
Margin: resources, clock, logic, memory, processor, performance, schedule, budget
Estimation: Resources, schedule, budget, staffing/manpower
Future design enhancement/expansion path
Architectural implementation
Validation verification

At a system engineering level, common mistakes generally occur when adequate design preparation and planning do not occur. The result is an unstable development effort where schedule slips and missed design objectives hamper the success of the project.
The resulting design failures occurring from these common mistakes impact design efforts and add significant risk. Usually, this haste is brought about by an overly aggressive schedule, a result of wishful thinking brought about by pressure to produce a product meeting unrealistic goals. Designers should avoid common mistakes resulting from aggressive schedule pressure. Following are some common design mistakes to watch for and avoid.

Common Design Mistakes

Starting an FPGA design in earnest before the requirements are sufficiently defined
System requirement changes that are not "rolled down" to the FPGA requirements
FPGA requirement updates that are not effectively communicated to the design team
Too many FPGA requirement changes
Significant FPGA requirement changes too far into the design cycle
Allowing too many people to change FPGA design requirements
Insufficient review of FPGA design change impacts
Poor or inconsistent HDL coding standard application
Poor or inconsistent HDL source structure (system architecture)
Poor or incorrect commenting of HDL source
Inefficient HDL coding style
Poor partitioning of design functionality between hardware and software functions
Poor partitioning of design functionality between fixed-function and programmable design components
Poor planning for design module and IP function block integration
Poor planning for design verification (debug & test)
Poor selection of design tools
Insufficient / Ineffective training of design team staff
Poor design documentation
Not enough design margin (resources, schedule, budget, personnel)
Poor design team staffing
Unclear design responsibility assignment
Allowing the same individual to implement and test a design module
Over-constraining a design
Poor or incomplete module-to-module interface within the FPGA device
Poor or incomplete FPGA to board-level signal and circuitry interface definition
Incomplete analysis or implementation of pre-configuration I/O signal state for FPGA I/O pins
Incorrect pin assignments at the FPGA component level
Incorrect FPGA device footprint signal, power or ground connectivity within the target board PCB
Overly aggressive design schedule
Performance requirements too close to the theoretical maximum performance of a family device or technology

4.2 常见的设计挑战和错误

FPGA设计错误可以定义为：在特定的FPGA器件内，没能达到资源利用率（I/O资源、逻辑资源、存储资源、硬IP资源、resource area）和性能（速率/功耗）要求的设计。开发并遵循一个优化的FPGA设计流程，就可以最小化FPGA设计中的错误和疏忽的数量及影响。这一流程应该定义明确的设计步骤、设计阶段目标和设计最终目标。它应该使FPGA设计周期得到管理并稳定下来。下面列出了与快速系统原型设计最相关的，影响FPGA设计的管理和开发过程的设计挑战。

常见的设计挑战：

1.
PCB版图设计

2.
PCB信号完整性设计

3.
FPGA外部时钟设计

4.
FPGA引脚分配

5.
设计余量：包括FPGA逻辑资源、时钟资源、存储器资源、内嵌处理器资源、性能、开发进度和经费

6.
设计预算：包括逻辑资源、进度计划、开发经费、开发人员的构成和数量

7.
设计功能的可增强和可扩展性设计

8.
设计功能的结构化实现

9.
设计功能的确认和验证

在系统工程层面看，哪一个阶段的设计准备和计划不充分，哪一个阶段通常就会出现常见的设计错误。这些设计错误使得开发过程变得不稳定。延期的设计进度和未能实现的设计目标阻碍了项目的成功。

常见的设计错误导致各种设计缺陷，这些设计缺陷增加了额外的设计工作量并且增加了显著的设计风险。欲速则不达，不切实际的产品生产目标导致了过度的压力，过度的压力使设计者不能切实地估计开发过程中的困难，从而制定出过于紧张的开发进度表。设计者应该避免由紧张的开发进度压力导致的常见设计错误。下面列出了应该注意和避免的常见设计错误。

常见的设计错误：

1.
在FPGA设计需求未充分明确的情况下，急迫地开始FPGA设计

2.
变更后的系统需求，没能细化为FPGA设计需求

3.
更新后的FPGA设计需求，没能有效地传达给设计团队

4.
太多的FPGA设计需求变更

5.
在设计过程的后期提出显著的FPGA设计需求变更

6.
允许太多的人改变FPGA设计需求

7.
对FPGA设计需求变更产生的影响缺乏评审

8.
对HDL编码标准的使用欠佳或前后不一致

9.
源代码结构（系统层次结构）欠佳或前后不一致

10.
对HDL源代码的注释欠佳或不正确

11.
低效率的HDL编码风格