原创 how to improve the efficiency of External Memory

2014-8-27 20:05 1065 10 11 分类: FPGA/CPLD

Nowadays, External Memorys(DDR2/DDR3) are widely used for data storage in communication system/video processing systems.

Even though the technolofy is developed very fast,it still can't satisfy the high data throughout requirement.

In this artical, we are trying to analysis how to improve the efficiency of the memory。

1)The bandwidth:

Bandwidth = DDR SDRAM bus width × 2 × frequency of operation × efficiency.

For example, running a 16-bit DDR SDRAM interface at a frequency of 100 MHz:
Bandwidth = 16 bits × 2 clock edges × 100 MHz × efficiency

2)The efficiency:

Efficiency = number of active cycles of data transfer/total number of cycles.

Factors affecting efficiency:

 

  1. The interface standard specified by the memory vendor
  2. The way that you transfer data.
interface standard:
Activate:Reading or writing to a closed row
has negative impact on the efficiency as the controller has to first activate that row and then wait until
tRCD time to perform a read or write.
Pre-charge:Switching a row
has a negative impact on the efficiency as you must first precharge the open row, then activate the next row and wait tRCD time to perform any read or write operation to the row.
Device CAS Latency:The higher the CAS latency, the less efficient an individual access.
Refresh
 
Bank Management efficiency
The following methods of data trasfer affect the efficiency:
  1. Performing individual read or write accesses is less efficient.
  2. Switching between read and write operation has a negative impact on the efficiency of the controller.
  3. Performing read or write operations from different rows within a bank or in a different bank
Ways to Improve Efficiency
To improve the efficiency of your controller, you can use the following tools and methods:
• DDR2 SDRAM Controller
• Auto-Precharge Commands
• Additive Latency
• Bank Interleaving
• Command Queue Look-Ahead Depth
• Additive Latency and Bank Interleaving
• User-Controlled Refresh
• Frequency of Operation
• Burst Length
• Series of Reads or Writes

文章评论1条评论)

登录后参与讨论

hot.summer_2010_438634915 2014-8-27 05:40

支持
相关推荐阅读
用户1778167 2016-03-30 20:56
上升沿和下降沿触发小论
这是刚开始学习FPGA时候,积累的一点资料。 具体如下,其实作者强调了在用FPGA做设计的时候,要注意同步设计,盲目的使用 信号做时钟,在时序分析上有很大问题,隐含着很大风险。   ...
用户1778167 2014-08-28 17:03
Memory interface generator(Xilinx,develop based on UI interface)
The details pls check the attachment....
用户1778167 2014-08-27 21:07
The difference between RDIMM/UDIMM/SO-DIMM/FBDIMM and LRDIMM.
There are many memory modules ,such as RDIMM,UDIMM,SO-DIMM,FBDIMM and LRDIMM. What is the differen...
我要评论
1
10
关闭 站长推荐上一条 /2 下一条