原创 师兄教诲

汤坚师兄言：要从一开始就养成良好的代码编写习惯。切记，谨记。。

还有，对不明朗的问题，要深究，弄清楚，比如警告信息的来源。。

下为初改代码，仍有不足，仅作纪念

module LCD(D, RS, RW, E, mclk, reset, state);
 input mclk, reset;
 output [7:0] D;
 reg    [7:0] D;
 output  RS, RW, E;
 reg     RS, RW, E;
 reg    [10:0] count;
 wire   clk;
 output [3:0] state;
 reg    [3:0] state;
 reg    [3:0] nextstate;
 
always @ (posedge mclk or negedge reset)
begin
if (!reset) count = 11'b0;
else count = count + 11'b1;
end

assign clk = count[10];

always @(posedge clk)
begin
 if (!reset) state <= 4'b0;
 else  state <= nextstate;
end

always @(state)

begin
     case (state)
      0:begin E <= 1'b0; RS <= 1'b0; RW <= 1'b0; D<=8'b00111000; nextstate <= 4'h1; end
      1:begin E <= 1; nextstate <= 4'h2; end
      2:begin E <= 1'b0; RS <= 1'b0; RW <= 1'b0; D<=8'b00000001; nextstate <= 4'h3; end
      3:begin E <= 1; nextstate <= 4'h4; end
      4:begin E <= 1'b0; RS <= 1'b0; RW <= 1'b0; D<=8'b00001110; nextstate <= 4'h5; end
      5:begin E <= 1; nextstate <= 4'h6; end
      6:begin E <= 1'b0; RS <= 1'b0; RW <= 1'b0; D<=8'b00000110; nextstate <= 4'h7; end
      7:begin E <= 1; nextstate <= 4'h8; end

      8:begin E <= 1'b0; RS <= 1'b0; RW <= 1'b0; D<=8'b10000000; nextstate <= 4'h9; end
      9:begin E <= 1; nextstate <= 4'hA; end
     10:begin E <= 1'b0; RS <= 1; RW <= 1'b0; D<=8'b01000001; end
     default:nextstate <= 4'h0;
 endcase
end
endmodule