原创 easyFPGA 简单分频时序逻辑电路

// half_clk.v
module half_clk(reset, clk_in, clk_out);
    input   clk_in, reset;
    output  clk_out;
    reg     clk_out;

    always @(posedge clk_in)
        begin
            if (!reset) clk_out = 0;
            else        clk_out = ~clk_out;
        end
endmodule

// testbench.v
`timescale 1ns/100ps
`define clk_cycle 50
module testbench;
    reg     clk, reset;
    wire    clk_out;

    always  #`clk_cycle     clk = ~clk;

    initial
        begin
            clk = 0;
            reset = 1;
            #10 reset = 0;
            #110 reset = 1;
            #100000 $stop;
        end
    half_clk half_clk_0(.reset(reset), .clk_in(clk), .clk_out(clk_out));
endmodule