原创 easyFPGA 计数分频时序电路

// fdivision.v
module fdivision(RESET, F10M, F500K);
    input   F10M, RESET;
    output  F500K;
    reg     F500K;
    reg [2:0]   j;
   
    always @(posedge F10M)
        if (!RESET)
            begin
                F500K <= 0;
                j <= 0;
            end
        else
            begin
                if (j == 5)
                    begin
                        j <= 0;
                        F500K <= ~F500K;
                    end
                else
                    j <= j + 1;
            end
endmodule

// fdivision_test.v
`timescale 1ns/100ps
`define clk_cycle 20

module fdivision_test;

    reg     F10M, RESET;
    wire    F500K_clk;

    always #`clk_cycle  F10M = ~F10M;

    initial
        begin
            RESET = 1;
            F10M = 0;
            #100 RESET = 0;
            #100 RESET = 1;
            #10000  $stop;
        end
    fdivision fdivision_0(.RESET(RESET), .F10M(F10M), .F500K(F500K_clk));
endmodule