SYNOPSYS Design Compiler
Usage Guidelines

1. 
Design Objects(term definition)

-         
DESIGN : A circuit that
performs one or more logical functions

-         
CELL : An instance of a design
or library primitive within another design

-         
REFERENCE : The name of the
original design that a cell instance “points to”

-         
PORT : The input or output of a
design

-         
PIN : The input or output of a
cell

-         
NET : The wire that connects
ports to pins and/or pins to each other

-         
CLOCK : A timing reference
object in Design Compiler memory which describes a waveform for timing analysis

2. 
Libraries

-         
target_library : describes the cells you’re
map to (.db file)

-         
link_library : describes cells you’ve
instantiated, and any wire load or operating condition models you are using
(.db file)

-         
symbol_library : contains symbols(.sdb
file) for the GUI’s schematic viewer

-         
synthetic_library : contains soft
macro(.sldb file) to implement math functions

-         
design_lib : Holds intermediate format
descriptions of your HDL code for design reuse;(really just a pointer to a
subdirectory)

3. 
Design_Analyzer

3?? ??? setup
file(.synopsys_dc.setup)? ????.

-         
1^st :
$SYNOPSYS/admin/setup directory

-         
2^nd : User’s home
directory

-         
3^rd : User’s current
working directory

4. 
Synthesizing

File ->
Read(or Analyze -> Elaborate) : Check syntax and synthesizability and builds
the design in DC memory using generic components(GETCH)

5. 
Timing Constraint

-         
at DC_SHELL

create_clock –period
10
find (port, “clk”)

set_don’t_touch_network
find (clock, “clk”)

set_input_delay –max
6 –clock
clk all_inputs() - find (port, “clk”)

(clk, except for
all the input port)

set_output_delay
–max 6
clock clk all_outputs()

-         
at Design_Analyzer

create_clock : Select the
clock source(port/pin) from Design Analyzer’s Symbol View

e     
Click the menus : Attributes
-> Clocks -> Specify ….

set_input_delay : Select
the port(s) to constrain from DA’s Symbol View

e     
Click the menus : Attributes
-> Operating Environment -> Input Delay

set_output_delay : Select
the port(s) to constrain from DA’s Symbol View

e     
Click the memus : Attributes
-> Operating Environment -> Output Delay

set_max_area

e     
=> Click the menu :
Attributes -> Operating Environment -> Area

Useful Command

-         
reset_design : current_design?? attributes? constraints? ??

-         
remove_design : DC memory??? design? ??

-         
list –libraries : DA memory? ?? ?? libraries? library name? file name? ????

-         
report_design : check wire
loads & operating conditions

-         
report_port –verbose : ?/?? ??? ??? attributes? constraints? ????(set_load,
set_drive, set_driving_cell, set_input_delay, set_output_delay..)

-         
report_clock :  current_design? ?? clock
objects? source, waveform ??? period? ????.

-         
report_lib libname : libname? ?? library
report? ????.(vendor-supplied operating conditions list)

-         
write_script : ??? ? ?? script???? design? ?? constraints? attributes? ??

6. 
Environmental Attributes

-         
set_operating_conditions : defines the operating conditions for the current
design(temperature, voltage, net parasitics)

      
temperature: best -> nominal -> worst (temperature increase, the delay
increases)



       voltage: best -> nominal -> worst
(voltage reduction, delay increase)

       process: best -> nominal -> worst
(fair increases, delay increases) 哦

       report_lib libname

       set_operating_conditions-max
"typ_-40_4.50"

 Set_driving_cell:
models a library cell driving the inputs ports

       This menu is not the DA.

       set_driving_cell-cell "ND2" find
(port in1)

Set_load: sets the load
value on ports and nets, specify the capacitive load on ports (default value is
0,

    load_of: technology library that is defined in the cell from
the specified input capacitance pin back)

    set_load 5 find (port out1) - Output port (out1) is a
five-unit load in 哦

    set_load load_of (lib / cell / pin) find (port out1) -
Output port (out1) of the load in the technology library gate

    (lib / cell / pin) is the.

    set_load load_of (lib / cell / pin) * 3 find (port out1)

     * Set_wire_load: sets the wire load model for the
current design

       net in the RC delay of the factors that
affect the "net_length, net fanout, # of 'sharp turns' of a net (through
metal layers or across metal layer), # of nearby nets (parasitic R & C), #
of nearby ground planes , freq of switching on nearby nets .. "but you
know you can not finish the layout. Therefore, the estimate should be. How?
This process, based on the statistical figures provided by the vendor will use
the model.set_wire_load “tc6a120m2”

ex)

current_design =
“my_design”

include
timing_budget.scr

/* assume a week
driving buffer on the inputs */

set_driving_cell
–cell IVA all_inputs() – find (port, *clk*)

/* limit input
load */

max_input_load =
load_of(cba/AND2/A)*10                 --
10 AND2 gate

set_max_capacitance
max_input_load all_inputs() – find(port, *clk*)

/* model the max
possible load on the outputs */

set_load
max_input_load*3 all_outputs()               --
3 subsequent inputs

7. 
exercise(script file)

/* Environment */

resert_design

create_clock –period 8 –name
sysclk find(port, clk*)  -- 125MHz clock

set_don’t_touch_network
find(clock, sysclk)

set_operating_conditions –max
typ_85_45                  -- typical, 85
degrees, 4.5v

set_wire_load tc6a120m2                               -- vendor
supplied model

/* time budget */

set_input_delay –max 4.8 –clock
sysclk all_inputs() – find(port, clk*)          --
clock? 40% alaks

set_output_delay –max 4.8
–clock sysclk all_outputs()                 --
“    “

/* load budget */

set_driving_cell –cell
BUF_A all_inputs() – find(port, clk*)          --
week driving

BASE_INPUT_LOAD
= load_of(cba_core/BUF_E/IA)                           --
redefine

set_max_capacitance
BASE_INPUT_LOAD*10 all_inputs() – find(port, *clk*)

set_load BASE_INPUT_LOAD*4 all_outputs() – find(port, clk*)

8. 
DC_SHELL vs. DESIGN_ANALYZER

-         
dc_shell : command line
interface

-         
design_analyzer : menu driven
interface

-         
dc_shell? ?? design_compiler
??

unix_prompt> dc_shell <CR>

dc_shell> command

or
unix_prompt> dc_shell –f
script_file_name.script

-         
VARIABLE

setting_variable

dc_shell>
VARIABLE_NAME = value   -- real number,
integer, list, string

          
       offset = 7.0

               index = 8

               short_list = {blk1, blk2, blk3}

               output_file = “test_rpt”

create lists :
using braces

dc_shell>
list_all = {blk1 blk2, “blk3”}  -- separate
: space or comma

double quotes
are optional

         dc_shell>
list_add = list_all + blk4     -- {“blk1”,
“blk2”, “blk3”, blk4”}

         dc_shell>
list_sub = list_all – blk3     -- {“blk1”,
blk2”}

-         
general
script method

user preference
: .synopsys_dc.setup      -- in home
directory

project specific
information : .synopsys_dc.setup  -- in
project directory

generic
constraints budget : scripts/constraints.scr

master compile
script : /scripts/run_it.scr

9. 
Optimization

-         
Architectural Optimization

high-level
synthesis : is based on design constraints and coding style

DesigWare
Implementation Selection : Use Synthetic_library( soft macros, technology
independent)

Sharing Common
Sub Expression

Resource Sharing

Reordering
Operators

-         
Logic-Level Optimization

Circuit function
is represented by GTECH parts

Structuring :
the use of intermediate terms to create a multilevel implementation of a
design,

is constrainted-based

useful for speed as well as area optimization,

Flattering : the
reduction of combination logic paths to a two-level(sum-of-products circuit),

useful for speed optimization(may be very area-intensive)

is done independent of constraints

         default
: structuring is enabled, flattening is disabled

         command
: set_structure (true | false)

                    set_flatten (true | false)

                   ex)
set_flatten true –effort low|medium|high

-         
Gate-Level Optimization

Combinational
Mapping : the process of using gates from the target library to generate a
design that meets timing

                       and
area goals

Sequential
Mapping : process by which DC maps to sequential cells from the technology
library

                         tries to save speed and
area by using a more complex sequential cell

10.     
Compiling a Hierarchy

-         
first phase : maps all blocks
to gates without regard to constrains, reserve hierarchy

-         
second phase : optimize logic
to meet timing and area constraints, fix violations across hierarchical
boundaries

-         
multiple instances

Only one copy of
design_block exists in DC memory

UNIQUIFY : makes
a copy of the referenced design for each instance

               each instance gets a unique
design name

               DC can map each instance to its
own specific environment

COMPILE+DON’T
TOUCH

               constrain and compile
multiple_design

               place
a don’t_touch attribute on the compiled multiple_design

               compile full_design

ex) d_design has
two a_design instance

      read –f db d_design.db

      current_design a_design

      include a_constraint.scr

      compile

      current design d_design

      set_don’t_touch find(design, a_design)

      include d_constraint.scr

      compile

-         
Compile Technique(Top-down,
Bottom-up)

Top-Down : read in the entire design hierarchy

               resolve multiple instatiations

               apply top-level constraints

               compile

               asses result

               save design

ex) top_down.scr

      analyze –format vhdl {t1.vhd, t2.vhd, …,
top.vhd}

      elaborate top

      uniquify

      include top_constraint.scr

      compile

      report_constraint –all > top_cons.rpt

      write –hierarchy –output top.db

      quit

11.     
Fault Coverage

Fault_Coverage = number of detectable faults / total
number of possible faults

-         
controllability : ability to
set internal nodes to a specific value

-         
observability : ability to
propagate the fault effect from internal node to a primary output port

-         
SCAN CHAIN : inserting a scan
chain involves replacing all flip-flop with scannable flip-flops with mux.

initialize nets
within the design(adds controllability)

capture results
from within the design(adds observability)

larger area than
non-scan register, larger setup time requirement, additional fanout &
capacitive loading

-         
one-pass scan synthesis

regular
registers are replaced with scannable ones, but not chained

include the scan style in the constraint script file

   set_scan_configuration –style
multiplexed_flip_flop

perform one-pass test scan compile

   compile –scan

-         
design for test

check_test :
return the status

create_test_patterns
: activate the ATPG function of DC