原创 占空比为1：1的2的幂次分频电路 VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CLK_DIV IS
    PORT(CLK:IN STD_LOGIC;
        RST: IN STD_LOGIC;
        CLK_2D:OUT STD_LOGIC;
        CLK_4D:OUT STD_LOGIC;
        CLK_8D:OUT STD_LOGIC;
        CLK_16D:OUT STD_LOGIC);
END CLK_DIV;

ARCHITECTURE BEHAVE OF CLK_DIV IS
SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN

   PROCESS(RST,CLK)
   BEGIN
   IF(RST='1') THEN
       COUNT <= "0000";
       ELSIF RISING_EDGE(CLK) THEN
           IF (COUNT = "1111") THEN
               COUNT <= (OTHERS => '0');
               ELSE
               COUNT <= COUNT + '1';
           END IF;
       END IF;
   END PROCESS;
  
   CLK_2D <= COUNT(0);
   CLK_4D <= COUNT(1);
   CLK_8D <= COUNT(2);
   CLK_16D <= COUNT(3);
END  BEHAVE;