原创 基于DE1的SRAM测试

     该测试的功能主要测试DE1的sram驱动,用一个拨码开关设置sram的读和写，当写入sram时，连续的写入，大约60ns写一次，当拨码开关设置成读时，就读出最后写的数据，在两位数码管中显示。所以读出的数据是随机的，没有按照固定的时间去读，而是随操作者的拨码开关而定。

      因为DE1的sram是512K大小的，型号为IS61Lv25616，字宽为16位，而本测试只需要能读写sram，所以只用到了其中的低8位，它的数据位有两个控制脚，分别为LB和UB，所以在程序中将UB一直设为1，不用。

      其引脚功能分布如下：

Clk50Mhz---------------------------------------------fpga的clk时钟

RstN--------------------------------------------------复位按键信号

SwOe --------------------------------------------------拨码开关，为1时写

SramData----------------------------------------------控制sram的双向数据口

Hex0---------------------------------------------------数码管0，显示低4位

Hex1---------------------------------------------------数码管1，显示高4位

LedW--------------------------------------------------led红，写数据时指示

LedW--------------------------------------------------led绿，读数据时指示

SramLbN---------------------------------------------控制sram是否用低8位数据

SramUbN---------------------------------------------控制sram是否用高8位数据

SramWeN----------------------------------------------控制sram的写

SramOeN----------------------------------------------控制sram的输出

SramCeN----------------------------------------------选中sram芯片

SramAdr-----------------------------------------------sram的18位地址线

其代码如下：

module SramTest(Clk50Mhz,RstN,SwOe,SramData,Hex0,Hex1,LedW,LedR,

              SramLbN,SramUbN,SramWeN,SramOeN,SramCeN,SramAdr);

input Clk50Mhz,RstN,SwOe;

inout [7:0]SramData;

output [17:0]SramAdr;

output[6:0]Hex0,Hex1;

output LedW,LedR,SramLbN,SramUbN,SramWeN,SramOeN,SramCeN;

//only use the low 8 bit of the data,and chose the chip forever

assign SramLbN=1'd0;

assign SramUbN=1'd1;

assign SramCeN=1'd0;

assign SramOeN=1'd0;

//control the read or write signal

assign LedW=(SwOe==1)?1:0;       //when the toggle switch(SwWrite) is toggled,it will be '1',and the write from sram is enable

//assign LedR=(SwRead==0)?1:0;

//delay to insure the write timeing sequence

reg[1:0]Delay60Ns;

always@(posedge Clk50Mhz or negedge RstN)

    if(!RstN)Delay60Ns<=2'd0;

    else if(Delay60Ns==2'd3)

            Delay60Ns<=2'd0;

    else Delay60Ns<=Delay60Ns+2'd1;

//write for the sram

reg[7:0] r_SramData;

reg[17:0]r_SramAddr;

reg r_SramWeN;

reg r_SramOeN;

always@(posedge Clk50Mhz or negedge RstN)

    if(!RstN)

    begin

        r_SramOeN<=1'd1;

        r_SramWeN<=1'd1;

        r_SramData<=8'd0;

        r_SramAddr<=18'd0;

    end

    else if(LedW)              //read sram enable

    begin

        r_SramOeN<=1'd1;

        r_SramData<=r_SramData+8'd1;

        r_SramAddr<=r_SramAddr+18'd1;

        r_SramWeN<=1'd0;

        if(Delay60Ns==2'd3)

            r_SramWeN<=1'd1;

    end

    else //if(LedR)

    begin

        r_SramOeN<=1'd0;

        if(Delay60Ns==2'd3)

        r_SramWeN<=1'd1;     

    end

assign SramWeN=r_SramWeN;

//assign SramOeN=r_SramOeN;

assign SramAdr=r_SramAddr;

assign SramData=SwOe ? r_SramData:8'bZ;

//read for the sram   

reg[7:0] r_Hex;

always@(posedge Clk50Mhz or negedge RstN)

    if(!RstN)

        r_Hex<=8'd0;

    else if(!LedW)              //read sram enable

    begin

        if(Delay60Ns==2'd3)

            r_Hex<=r_SramData;

    end

//disply the number of reading sram

reg[6:0] r_Hex0,r_Hex1;

//always@(r_SramData)

always@(posedge Clk50Mhz or negedge RstN)

    if(!RstN)

    begin

        r_Hex0<=7'd0;

        r_Hex1<=7'd0;

    end

    else if(!SwOe)

    begin

        r_Hex0<=SetHex(r_Hex[3:0]);

        r_Hex1<=SetHex(r_Hex[7:4]);

    end

assign Hex0=r_Hex0;

assign Hex1=r_Hex1;

//SetHex :function of encode

function [6:0] SetHex;

input[3:0] Number;

case(Number)

    4'd0: SetHex = 7'b100_0000; //0

    4'd1: SetHex = 7'b111_1001; //1

    4'd2: SetHex = 7'b010_0100; //2

    4'd3: SetHex = 7'b011_0000; //3

    4'd4: SetHex = 7'b001_1001; //4

    4'd5: SetHex = 7'b001_0010; //5

    4'd6: SetHex = 7'b000_0010; //6

    4'd7: SetHex = 7'b111_1000; //7

    4'd8: SetHex = 7'b000_0000; //8

    4'd9: SetHex = 7'b001_1000; //9

    4'd10: SetHex = 7'b000_1000; //A

    4'd11: SetHex = 7'b000_0011; //B

    4'd12: SetHex = 7'b100_0110; //C

    4'd13: SetHex = 7'b010_0001; //D

    4'd14: SetHex = 7'b000_0110; //E

    4'd15: SetHex = 7'b000_1110; //F

    default:SetHex = 7'b111_1111; //default

endcase

endfunction

endmodule

      注：在用altera的DE1开发板调试Sram驱动时，出现了上篇文章提出的错误：Error: BIDIR pin "SramData[0]" feeds BIDIR pin " renamed_port_9"。（弄了一天才发现是moudle模块中重复定义了SramData。），当把这个错误解决后，Sram的驱动也就成功了。