原创 综合出错请注意

1 每种情况下，即每一个case或if..else中都要把所有的输出列出来，否则会产生锁存器，锁存前面那个值，当然，目的是产生锁存器的除外。

2 综合中，不支持initial语句。同一个变量不能在两个always块中赋值。always中只能有一个赋值形式（block or non-block）always块中赋值的所有的信号必须有明确的值；否则，要加入锁存器来保持赋值前的最后一个值，否则综合器会发出警告，提示设计中插入了锁存器。

3 if..else和case语句放在always块中，repeat语句和while语句不可以综合。forever语句放在initial语句中，生成时钟等周期波形。

4 基于verilogHDL的数字系统应用设计（第2版）（王钿，卓兴旺编）书上有许多关于综合的知识。

5 CASE语句放在always块中，在begin和case之间，要对端口输出和中间变量nest_state进行复制，这样就不会有

@W: CL113 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Feedback mux created for signal wr.
@W: CL118 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Latch generated from always block for signal wr, probably caused by a missing assignment in an if or case stmt
@W: CL113 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Feedback mux created for signal rd.
@W: CL118 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Latch generated from always block for signal rd, probably caused by a missing assignment in an if or case stmt
@W: CL113 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Feedback mux created for signal mode.
@W: CL118 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Latch generated from always block for signal mode, probably caused by a missing assignment in an if or case stmt
@W: CL113 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Feedback mux created for signal inver.
@W: CL118 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Latch generated from always block for signal inver, probably caused by a missing assignment in an if or case stmt
@W: CL112 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Feedback mux created for signal dir. Did you forget the set/reset assignment for this signal?
@W: CL118 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Latch generated from always block for signal dir, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/moorefsm\moorefsm.v":54:8:54:11|Latch generated from always block for signal count[2:0], probably caused by a missing assignment in an if or case stmt

的情况了。这是因为出现了锁存器。

同样，对于if语句也是如此：

module fsmctl(bist_in,reset,flag,address,test,ena,erroraddress);
input bist_in,reset,flag;
input [17:0] address;
wire [17:0] address;
output [17:0] erroraddress;
output test,ena;
reg test,ena;
reg [17:0] erroraddress;
always@(bist_in or flag or reset or address)
begin
if(bist_in)
begin
    if(flag)
begin
    test<=1;
ena<=0;
erroraddress<=address;
end
    else
    begin
        test<=0;
        if(reset)ena<=0;
       else ena<=1;
end
end
else
begin
test<=0;
ena<=0;

end
end
endmodule

会出现这样的警告：

@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":12:0:12:1|Latch generated from always block for signal erroraddress[17:0], probably caused by a missing assignment in an if or case stmt

修改1：在倒数第四行上加上erroraddress<=18'bz;

会出现更多的警告

@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress_e, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[1], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[2], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[3], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[4], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[5], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[6], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[7], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[8], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[9], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[10], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[11], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[12], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[13], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[14], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[15], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[16], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:/Synplicity/qina/fsmctl\fsmctl.v":23:8:23:9|Latch generated from always block for signal erroraddress[17], probably caused by a missing assignment in an if or case stmt

修改2：将语句

always@(bist_in or flag or reset or address)

begin

if(bist_in)

该为

always@(bist_in or flag or reset or address)

begin
       erroraddress<=18'bz;
       if(bist_in)

就正确了。

6 既然有多重循环，那就加入循环语句。置位时都赋值为1.复位时都赋值为0.保持时不用写自动生成锁存器。

7 出现错误：

@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[15] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[14] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[13] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[12] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[11] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[10] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[9] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[8] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[7] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[6] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[5] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[4] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[3] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[2] is always 0, optimizing ...
@W: CL189 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Register bit data_in[1] is always 0, optimizing ...

是因为data_in为16位的，在开始定义时却定义成了一位的。

8 出现错误：

@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.
@N: CL177 :"C:/Synplicity/qina/jiekou\bist_mram_con.v":21:12:21:13|Sharing sequential element data_in_e.

是因为：前面的复位时，data_in<=16'bz;

若该为： data_in<=16'b0;则可避免出现这样的错误。

9 多个模块综合成一个模块时，只把顶层模块放入synplify pro中即可，放多了会出现错误的。

@W: CL113 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Feedback mux created for signal j[10:0].

@W: CL118 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Latch generated from always block for signal j[10:0], probably caused by a missing assignment in an if or case stmt

@W: CL113 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Feedback mux created for signal i[10:0].

@W: CL118 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Latch generated from always block for signal i[10:0], probably caused by a missing assignment in an if or case stmt

@N: CL177 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Sharing sequential element i.

@N: CL177 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Sharing sequential element i.

@W: CL113 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Feedback mux created for signal pointer[1:0].

@W: CL118 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Latch generated from always block for signal pointer[1:0], probably caused by a missing assignment in an if or case stmt

@W: CL113 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Feedback mux created for signal start_march.

@W: CL118 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Latch generated from always block for signal start_march, probably caused by a missing assignment in an if or case stmt

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <9> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <8> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <7> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <6> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <5> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <4> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <3> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <2> of j[9:0]

@W: CL171 :"D:/Modeltech_6.2e/qina8\yuansukongzhi.v":66:5:66:8|Pruning Register bit <1> of j[9:0]

这些错误，代码中加上红色字体部分就可以了，因为case的状态中有，而case外没有，产生了锁存器。

always@(current_state or end_march)

begin

     next_state<=idle;

     //{wr,dir,minus}<=3'b110;

     {wr,dir}<=2'b11;

       data_s<=0;

       i<=11'h000;

       j<=11'h000;

       pointer<=2'b00;

       start_march<=0;

     case(current_state)

有时生成的触发器不符合标准，可能是因为always@()中的触发沿设置反了。

    spnplify 与 XST 综合结果的一个差异 。—（转自songsong 的空间，谢谢！）

       这些天使用synplify pro综合，发现了一些与XST不同的地方，也就是synplify和xst之间的差异。

示例如下：

code :

module try(
                   clk,
                   rst,
                   in,
                   out
);
input     clk,rst;
input     [3:0] in;
output [3:0] out;

reg [3:0]out;
reg tmp;

always @(posedge clk or posedge rst)begin
               if(rst) out <= 4'h0;
               else if(tmp) out <= 4'hA; //注意这句
               else out <= in;
end

endmodule

    synplify综合的log:

@W: CG133 :"D:\try\try.v":12:4:12:6|No assignment to tmp
@W: CL190 :"D:\try\try.v":14:0:14:5|Optimizing register bit out[0] to a constant 0
@W: CL190 :"D:\try\try.v":14:0:14:5|Optimizing register bit out[2] to a constant 0
@W: CL171 :"D:\try\try.v":14:0:14:5|Pruning Register bit <2> of out[3:0]

@W: CL171 :"D:\try\try.v":14:0:14:5|Pruning Register bit <0> of out[3:0]

@W: CL159 :"D:\try\try.v":8:13:8:14|Input in is unused

Technology View :

     synplify的综合结果表现为：reg类型的信号tmp没有赋值，把信号 in 优化掉了。    

     XST的综合的log :

WARNING:Xst:653 - Signal <tmp> is used but never assigned. Tied to value 0.

      显然，XST是把信号tmp优化掉了。这就是区别，也是导致我刚开始用synplify综合，总是和ISE综合结果不同的根本原因。（还是用chipscope观测出来的）

    另外，如果把信号tmp的类型改成 wire。2个工具的综合结果就一样了，都是把tmp优化掉。

改成wire后的Technology View :

        折腾半天才发现这个问题，如有错误，请高手指出，谢谢。