原创 Nadamuni Says

As process geometries grow smaller, the equipment required to produce the nanometer sized features on the silicon substrate become more and more expensive. This raises a big question. Who pays for the research and development effort required to create the equipment and processes that enable such deep sub micron designs to be manufactured? The leading stakeholders in the semiconductor industryIDMs, foundry companies, fabless semiconductor vendors and semiconductor equipment manufacturing companies, among othershave formed alliances and consortia all aimed at creating a pool of research that can be commercialized and productized to benefit all the stakeholders at the same time. Some of these alliances compete with each other. Others are loose alliances where members can be part of one or more consortium. At the end of the day, the question is whether the IDMs that have captive fabs are more equal than their partners because they have a chance to conduct and test internal tools and processes before those processes become mainstream and are available to the foundries and the fabless vendors.

The news that NXP (Phillips Semiconductor) may not participate in the Crolles2 consortium brings some of these issues to the forefront. How strong are these alliances? Is it an alliance of equals?

The other important factor to be considered is tools related. Will all of the design tools, process improvement tools, yield management tools and other tools essential for the continuation of Moore's law, come from the EDA industry or are the foundries and IDMs going to have to start investing heavily in internal tool development. The reference design model worked very well all these years through a few generations of process nodes. Will this continue?