原创 sram程序

Library IEEE; Use IEEE.Std_logic_1164.all; USe IEEE.Std_logic_unsigned.all; ENTITY sram IS GENERIC ( k: integer:=8; --8位数据宽度 w: integer:=4 --4位宽度地址，共16个地址 ); PORT ( rd,wr,cs: IN STD_LOGIC; --定义写，读，片选控制信号 adr: IN STD_LOGIC_VECTOR(w-1 DOWNTO 0); --4位地址信号 din: IN STD_LOGIC_VECTOR(k-1 DOWNTO 0); --8位输入信号 dout: OUT STD_LOGIC_VECTOR(k-1 DOWNTO 0) --8位输出信号 ); END sram ; ARCHITECTURE behave OF sram IS subtype word is STD_LOGIC_VECTOR(k-1 DOWNTO 0); type memory is array(0 to 2**w-1) of word; signal sram:memory; --定义中间缓存空间 signal adr_in:Integer; --定义地址指向标志 BEGIN adr_in<=conv_integer(adr); --将输入地址转换为地址指向标志 Write: process(wr,cs,adr_in,din,rd) --数据写入进程：Write begin if wr='0' then if cs='0' and rd='1' then sram(adr_in)<=din; end if; end if; end process; Read: process(rd,cs,adr_in,wr) --数据读入进程:Read begin if(rd='0' and cs='0' and wr='1') then dout<=sram(adr_in); else dout<=(others=>'Z'); end if; end process; end behave;