原创 10分频 源代码与仿真激励

本代码为EDA工具的实验代码。

有些有特定的编码规则（如用finish不用stop, 不加`timescale  1ns\1ps等）

module fp(clk,rst_n, fm);
input  clk;  
input rst_n;  
output fm;
reg [3:0] cnt;

always @(posedge clk or negedge rst_n)
   if(!rst_n)  cnt<=0;
   else if(cnt==4'd9)  cnt<=4'd0;
        else       cnt<=cnt+1;
assign fm = ( cnt<4'd5 ) ? 1'd0: 1'd1;

endmodule

`timescale 1 ns/ 1 ps
module fp_test;
reg clk;
reg rst_n;
wire fm;
                       
fp i1 (
  .clk(clk),
  .fm(fm),
  .rst_n(rst_n)
);
initial begin                                                                                        
   clk=0;
   forever
         #10 clk=~clk;                       
end                                                   

initial   begin                                                 
     rst_n=1;
     #10  rst_n=0;
     #10  rst_n=1;
     #500  $finish;
                                               
end     
/*initial begin
  $shm_open("fp.shm");
  $shm_probe("AS");
  #1000 $shm_close;
end
*/
/*
initial begin
  $fsdbDumpfile("fp.fsdb");
  $fsdbDumpvars();
end  */
/*initial begin
  $vcdplusfile("fp.vcd");
  $vcdpluson;
  $vcdplustraceon;
end
  */                                             
endmodule